Verilog HDL code and documentation for pipelined RISC-V processors designed as a minor project by a team of 4. Includes testbench files, documentation, and sample programs. Completed as part of our 6th semester coursework. Data-path for the different types of instructions are being created, later every data path will be combined together to make a complete RISC-V CPU.
SudeepJoshi22/Minor-Project-2023-RISC-V-processor
Verilog HDL code and documentation for pipelined RISC-V processors designed as a minor project by a team of 4. Includes testbench files, documentation, and sample programs. Completed as part of our 6th semester coursework.
VerilogMIT