SudeepJoshi22

RISCV-MYTH-Workshop-contents-by-Sudeep-Joshi

RISCV-MYTH Workshop contents by Sudeep Joshi.

SWIS-V

A Single Cycle RISC-V core supporting RV32I Instruction Set.

CORDIC_Unit

CORDIC Unit Design and Synthesis Using Verilog HDL and YOSYS

DHRUT-V

5-Stage Pipelined Custom RISC-V core

FFT_HARDWARE

FFT Hardware written in TL-Verilog.

Minor-Project-2023-RISC-V-processor

Verilog HDL code and documentation for pipelined RISC-V processors designed as a minor project by a team of 4. Includes testbench files, documentation, and sample programs. Completed as part of our 6th semester coursework.

Qm.n-and-Integer-Interconversions

Signed Integer to Qm.n binary conversion and vice versa written in Python.

Small_Projects

SudeepJoshi22

Config files for my GitHub profile.

SudeepJoshi22/Minor-Project-2023-RISC-V-processor

Verilog HDL code and documentation for pipelined RISC-V processors designed as a minor project by a team of 4. Includes testbench files, documentation, and sample programs. Completed as part of our 6th semester coursework.

SudeepJoshi22/CORDIC_Unit

CORDIC Unit Design and Synthesis Using Verilog HDL and YOSYS

SudeepJoshi22/DHRUT-V

5-Stage Pipelined Custom RISC-V core

SudeepJoshi22/FFT_HARDWARE

FFT Hardware written in TL-Verilog.

SudeepJoshi22/Qm.n-and-Integer-Interconversions

Signed Integer to Qm.n binary conversion and vice versa written in Python.

SudeepJoshi22/Small_Projects

SudeepJoshi22/SudeepJoshi22

Config files for my GitHub profile.