Pinned Repositories
AccDNN
A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
Accelerating-CNN-with-FPGA
This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.
Awesome-Federated-Learning
Federated Learning Library: https://fedml.ai
CNN-FPGA
使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用
CNN-FPGA-1
CNN-On-FPGA
FPGA
CNN_for_SLR
A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.
cnn_hardware_acclerator_for_fpga
This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs
Communication-Matlab
对通信原理的内容的matlab实现
Must-Reading-on-ISAC
Must Reading Papers, Research Library, Open-Source Code on Integrated Sensing and Communications (aka. Joint Radar and Communications, Joint Sensing and Communications)
TongGeTT's Repositories
TongGeTT/Must-Reading-on-ISAC
Must Reading Papers, Research Library, Open-Source Code on Integrated Sensing and Communications (aka. Joint Radar and Communications, Joint Sensing and Communications)
TongGeTT/AccDNN
A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
TongGeTT/Accelerating-CNN-with-FPGA
This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.
TongGeTT/Awesome-Federated-Learning
Federated Learning Library: https://fedml.ai
TongGeTT/CNN-FPGA
使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用
TongGeTT/CNN-FPGA-1
TongGeTT/CNN-On-FPGA
FPGA
TongGeTT/CNN_for_SLR
A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.
TongGeTT/cnn_hardware_acclerator_for_fpga
This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs
TongGeTT/Communication-Matlab
对通信原理的内容的matlab实现
TongGeTT/convolution_network_on_FPGA
CNN acceleration on virtex-7 FPGA with verilog HDL
TongGeTT/conways-game-of-life
A Verilog implementation of Conway's Game of Life
TongGeTT/DeepLearning-TensorFlow2
本专栏我将使用谷歌TensorFlow2.0框架逐一复现经典的卷积神经网络：LeNet、AlexNet、VGG系列、GooLeNet、ResNet 系列、DenseNet 系列，以及现在比较流行的：RCNN系列、SSD、YOLO系列等。
TongGeTT/dfl-pens
Decentralized federated learning of deep neural networks on non-iid data
TongGeTT/DW2TF
Darknet Weights to TensorFlow
TongGeTT/HLS-LeNet
The CNN based on the Xilinx Vivado HLS
TongGeTT/Image-Classification-using-CNN-on-FPGA
Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.
TongGeTT/keras-yolo3
A Keras implementation of YOLOv3 (Tensorflow backend)
TongGeTT/mnist-nnet-hls-zynq7020-fpga
to illustrate how to removal a Neural Network from pc to FPGA board ,it contain all the code include c code worked in pc,HLS prj accelerate code in FPGA,and implacement in block design and with SDK app......
TongGeTT/netron
Visualizer for neural network, deep learning, and machine learning models
TongGeTT/Tiny_YOLO_v3_ZYNQ
Implement Tiny YOLO v3 on ZYNQ
TongGeTT/Ultra96-Yolov4-tiny-and-Yolo-Fastest
Yolov4-tiny and Yolo-Fastest (Tensorflow2) is used to detect vehicles on Ultra96-v2 board, and we support model pruning.
TongGeTT/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA
Verilog Generator of Neural Net Digit Detector for FPGA
TongGeTT/xfopencv
TongGeTT/Yolo-Fastest
:zap: Yolo universal target detection model combined with EfficientNet-lite, the calculation amount is only 230Mflops(0.23Bflops), and the model size is 1.3MB
TongGeTT/yolo_tensorflow
Tensorflow implementation of YOLO, including training and test phase.
TongGeTT/YOLO_tensorflow-1
tensorflow implementation of 'YOLO : Real-Time Object Detection'