TonyHo722

Pinned Repositories

Arduino
ESP8266 core for Arduino
Language:C++00
arduino-esp8266-alexa-multiple-wemo-switch
multiple belkin wemos switch emulator using ESP8266
Language:C++00
Arduino-IRremote
Infrared remote library for Arduino: send and receive infrared signals with multiple protocols
Language:C++00
areca-backup-release-mirror
Unofficial release mirror of Areca Backup
Language:Java00
artisan
artisan: visual scope for coffee roasters
Language:Python00
axilite-slave
Language:SystemVerilog00
fsic_tony
for fsic integration debug
Language:Verilog02
TC4-shield
Language:C++1 2 01
verilog-pcie
Verilog PCI express components
Language:Verilog10

TonyHo722's Repositories

TonyHo722/fsic_tony
for fsic integration debug
Language:Verilog02
TonyHo722/axil_axis
Language:Verilog
TonyHo722/bash_study
Language:Shell
TonyHo722/Caliptra
Caliptra IP and firmware for integrated Root of Trust block
TonyHo722/caravel-lab
Language:Verilog2
TonyHo722/caravel-lite
TonyHo722/caravel_mgmt_soc_litex
https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
Language:Verilog
TonyHo722/caravel_mgmt_soc_litex-tony
TonyHo722/caravel_user_project
https://caravel-user-project.readthedocs.io
Language:Verilog
TonyHo722/caravel_user_project_fsic
Language:Verilog1 0
TonyHo722/caravel_user_project_la_test1
Language:Verilog
TonyHo722/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
TonyHo722/cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
TonyHo722/fsic_asic
Language:Verilog
TonyHo722/fsic_fpga
Language:Ada0 0
TonyHo722/hackmd-io-issues
Reporting issues about HackMD Enterprise Edition and HackMD.io
TonyHo722/HLS-SOC-Discussions
Discussion Forum for High-Level Synthesis (HLS) Courses in Taiwan.
TonyHo722/linux-xlnx
The official Linux kernel from Xilinx
Language:C
TonyHo722/makefile_study
Language:Makefile
TonyHo722/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
TonyHo722/perl_study
Language:Verilog
TonyHo722/python
Python学习
TonyHo722/python_study
Language:Verilog
TonyHo722/rocket-chip
Rocket Chip Generator
TonyHo722/ssh_test
TonyHo722/systemverilog_study
Language:SystemVerilog1 0
TonyHo722/verilog_study
Language:Verilog
TonyHo722/vivado-risc-v
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
TonyHo722/yosys_study
Language:Verilog
TonyHo722/zephyr
Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.