USKYLD
I am Uskyld, a student in Harbin Institute of Technology university. I want to study in Github and try to make some contributions to the community.
Harbin Institute of Technology universityHarbin Institute of Technology university
USKYLD's Stars
xinntao/Real-ESRGAN
Real-ESRGAN aims at developing Practical Algorithms for General Image/Video Restoration.
YosysHQ/picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
weaigc/bingo
Bingo,一个让你呼吸顺畅 New Bing。
openhwgroup/cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
pulp-platform/axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
rsd-devel/rsd
RSD: RISC-V Out-of-Order Superscalar Processor
zachjs/sv2v
SystemVerilog to Verilog conversion
taichi-ishitani/tvip-axi
AMBA AXI VIP
mathis-s/SoomRV
A simple superscalar out-of-order RISC-V microprocessor
bluespec/Toooba
RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
LoveLonelyTime/Bergamot
An exquisite superscalar RV32GC processor.
dpretet/axi-crossbar
An AXI4 crossbar implementation in SystemVerilog
tommythorn/yarvi
Yet Another RISC-V Implementation
ispras/qdt
QEMU Development Toolkit
skudlur/diablo
diablo is an Out-Of-Order 64-bit RISC-V processor.
hplp/AES_implementations
AES implementations in chisel, PyRTL, VivadoHLS, C++ and Python
NazerkeT/MultilevelTLB
Multilevel TLB implementation workspace for (CVA6) Ariane Core during summer GSoC'21
JosephHanJL/RISCV_OoO
Out of order P6-style RISC-V processor