UniversityOfPlymouth-Electronics/DigitalSystems

Issues

• Finite State Machines - Moore Machines

  #21 opened 2 years ago
  1

• Missing negedge N_RESET

  #20 opened 2 years ago
  2

• Truth table incorrect?

  #16 opened 2 years ago
  1

• ASICs not covered

  #15 opened 3 years ago
  0

• Clock Dividers

  #14 opened 3 years ago
  0

• FPGA Specific Issues

  #13 opened 3 years ago
  0

• Section on Counters

  #12 opened 3 years ago
  0

• Add content about risks of Mealy Machines

  #11 opened 3 years ago
  0

• Fix links to lectures

  #10 opened 3 years ago
  0

• Consider different style counters and apploica

  #9 opened 3 years ago
  1

• Clock Dividers

  #8 opened 3 years ago
  0

• Wrong N value

  #6 opened 3 years ago
  0

• Wrong module name

  #5 opened 3 years ago
  0

• Image on first page is missing

  #4 opened 3 years ago
  0

• Links in TOC for both comb logic and comb_logic_components need fixing

  #3 opened 3 years ago
  0

• https://github.com/UniversityOfPlymouth-Electronics/DigitalSystems/blob/main/level5/comb_logic.md#task-204-logic-values

  #2 opened 3 years ago
  3

• Wrong video in getting started

  #1 opened 3 years ago
  0