Issues
- 0
Version.hh
#409 opened by dANW34V3R - 0
Fix up random buffer value generation.
#413 opened by tom91136 - 1
Got error when run aarch64's binary with SimEng
#411 opened by wkisme - 2
Set errno for simulated program
#410 opened by dANW34V3R - 1
- 3
- 1
- 0
Integrate BP update with in-order core
#407 opened by ABenC377 - 1
Incorporate new BP with in-order core
#406 opened by ABenC377 - 0
More registers required to rename all micro-ops than possible causes stalling
#400 opened by JosephMoore25 - 0
- 0
Add RISC-V compressed instruction support
#351 opened by dANW34V3R - 0
Uncaught config option errors
#391 opened by jj16791 - 0
bitfieldManipulate uncaught bound restrictions
#394 opened by jj16791 - 0
Boolean Config Parameter Output
#398 opened by dANW34V3R - 1
Ensure all Syscalls have regression tests
#342 opened by FinnWilkinson - 1
Fetch Unit Parameterisation
#397 opened by dANW34V3R - 0
Clean Up Instruction Class
#355 opened by FinnWilkinson - 1
`SimEng/src/lib/Elf.cc` missing cstdio
#386 opened by tom91136 - 0
Clean Up Core Class
#356 opened by FinnWilkinson - 1
Update generic branch predictor
#354 opened by ABenC377 - 0
Clean Up Architecture Class
#357 opened by FinnWilkinson - 1
Verify Config file parameters
#369 opened by JosephMoore25 - 0
Fix branch predictor flow (disappearing branches)
#390 opened by ABenC377 - 1
- 1
AArch64 ST1W test failure due to dirty page usage
#382 opened by jj16791 - 1
- 1
Clean Up / Replace CoreInstance.cc
#358 opened by FinnWilkinson - 0
- 1
[AArch64] Verify and fix FCVTZU execution logic
#365 opened by FinnWilkinson - 2
Update SimEng's Unit test suite
#340 opened by FinnWilkinson - 0
[AArch64] Create helper functions for Load and Store instruction execution logic
#378 opened by FinnWilkinson - 0
Config Docs Range and Core Type Clarifications
#376 opened by dANW34V3R - 1
Interface-Type restriction not applied
#372 opened by jj16791 - 0
Zero register destination operands in multi-destination register AArch64 instructions
#375 opened by jj16791 - 1
[AArch64] Fix sign extending
#371 opened by FinnWilkinson - 1
Add SME2 support
#349 opened by FinnWilkinson - 0
CloverLeaf RISC-V Infinity Issue
#359 opened by dANW34V3R - 0
- 0
Alias NYI exception can cause the incorrect rewinding of unrenamed physical registers
#362 opened by jj16791 - 0
Process memory not cleared between tests
#361 opened by jj16791 - 0
sve_merge_store_data doesn't account for source vector elements and destination memory elements being different widths
#360 opened by jj16791 - 0
- 0
Create a global "SimInfo" object
#345 opened by jj16791 - 0
Replace YAML.cpp with Rapid Yaml library
#344 opened by jj16791 - 0
- 1
Add RISC-V floating point support
#350 opened by dANW34V3R - 1
Overhaul the Jenkin's test pipeline
#341 opened by FinnWilkinson - 1
Incorrect logic on multiple SMSTART calls
#329 opened by FinnWilkinson - 0