Issues
- 0
Make project REUSE compliant
#20 opened by stv0g - 2
Irregular reads from DMA
#8 opened by stv0g - 0
Reduce size of PCIE BAR0 to 1M to avoid mapping issues when detecting the PCIe device post-bootup
#15 opened by stv0g - 2
- 2
- 0
Create overview table over different Aurora IP parameters for RTDS, OPAL-RT & FPGA partners
#14 opened by stv0g - 1
Xilinx-Ubuntu VM unreachable
#13 opened by stv0g - 0
Testing Aurora IP core with ZCU106 board
#10 opened by stv0g - 1
Dev - [closed]
#18 opened by stv0g - 4
Add AXI EMC controller to VC707 design for flashing bitstream into configuration memory via PCIe
#9 opened by stv0g - 1
- 11
WIP: New Makefile - [closed]
#16 opened by stv0g - 1
Upgrade hw_server on Ernie to Vivado 2019.1
#5 opened by stv0g - 2
Move aurora-rtds project into `ips` folder
#4 opened by stv0g - 2
Implement AXI_S_WSTRB logic
#7 opened by stv0g - 0
- 4
- 3
Licensing issue with Vivado 2019.1
#1 opened by stv0g - 0