VesselLee's Stars
suisuisi/FPGAandCNN
基于FPGA的数字识别-实时视频处理的定点卷积神经网络实现
rbshi/elstm
wkxfudan/booth
rcetin/booth_wallace_multiplier
Booth encoded Wallace tree multiplier
pareddy113/Design-of-various-multiplier-Array-Booth-Wallace-
wuzeyou/Multiplier16X16
Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder
ashwaninituk/Sigmoid-Calculation
Sigmoid Calculation using CORDIC algorithm in Verilog
sadrasabouri/CORDIC
Implementation of CORDIC Algorithms Using Verilog
NimaSamadi007/cordic_tanh
Tanh function implementation on hardware (FPGA), based on CORDIC algorithms
SidharthMehta/Tanh-unit
Created a Tanh gate for LSTM cell, a type of neural network using RTL with the goal of least area and execution time product
kasyap-pasumarthy/ECE-564-Project
Tanh module for LSTM
cxdzyq1110/NPU_on_FPGA
在FPGA上面实现一个NPU计算单元。能够执行矩阵运算(ADD/ADDi/ADDs/MULT/MULTi/DOT等)、图像处理运算(CONV/POOL等)、非线性映射(RELU/TANH/SIGM等)。
ayushgupta98/ALU
An efficient multiplier and Accumulator (MAC) unit to do operations like multiplication & addition on numbers stored in RAM unit attached to it.
brad-newby/Image_Recognition_Neural_Net_Node
This is a project for a university course in which I made a node of a neural net that can recognize a hand written character. The project utilizes Verliog and Vivado. The node is made up of a Multiplier Accumulator and a sigmoid block. The node uses the files digits_hex and weights_hex as inputs.
jogeshsingh/Shift-and-Add-Accumulator-Based-Multiplier-Design
This project includes 4 bit configuration of Datapath and controller of shift and add sequential multiplier design . It was designed in Xilinx VIVADO using Verilog HDL.
ihansam/2020_winter_proj
Implement Precision Scalable Multiplier-Accumulator Unit for Deep Learning Acceleration
daneshvar-amrollahi/Multiplier-Accumulator
A Verilog implementation of a multiplier accumulator (MAC) unit.
ChenJianyunp/Posit32-2-exact-multiply-accumulator
This is a hardware implementation of exact multiply accumulator for 32-bit posit number with es=2
andydo111/moded-systolic
Moded systolic array with modified MAC units.
smita181298/MACUnit
Multiplier Accumulator unit using booth multiplier and carry select adder
KailinLi/Washing-Machine
Washing Machine using Verilog HDL
bruceDuand/systolic_array_mac
rakeshgehalot/MAC_in_verilog
Low Power Multiplier Accumulator
technocrat13/32bit-MAC-Unit
32 bit Vedic Multiplier, using the Urdhava Triyagbhayam Sutra Criss Cross method, coded in Verilog
smanda25/MAC
MAC unit using Verilog
roo16kie/MAC_Verilog
Using verilog to implement MAC (Multiply Accumulate) . Verifying it by testbench .
Parimala6/Floating-point-MAC-verilog
32 - bit floating point Multiplier Accumulator Unit (MAC)
dldldlfma/super_small_toy_tpu
hsiehong/tpu
AIChip 2021 project, NCKU
vincent08tw/ai_on_chip_project1
tpu-systolic-array-weight-stationary