VesselLee

VesselLee's Stars

• bytedance/ic_flow_platform

  IFP (ic flow platform) is an integrated circuit design flow platform, mainly used for IC process specification management and data flow contral.

  Language:Python14733

• google/sky90fd-pdk

  10213

• google/skywater-pdk

  Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

  Language:Python2.9k378

• google/gf180mcu-pdk

  PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).

  Language:Makefile35254

• google/open-source-pdks

  Index of the fully open source process design kits (PDKs) maintained by Google.

  827

• circuitnet/CircuitNet

  CircuitNet: An Open-Source Dataset for Machine Learning Applications in Electronic Design Automation (EDA)

  Language:Python25739

• krzhu/abc_py

  Simple Python interface for ABC

  Language:C++207

• krzhu/abcRL

  MLCAD 2020: Reinforcement for logic optimization sequence exploration

  Language:Python248

• berkeley-abc/abc

  ABC: System for Sequential Logic Synthesis and Formal Verification

  Language:C847522

• kunalg123/icc2_workshop_collaterals

  This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efabless Corp. Pvt. Ltd. VSD has not checked functionality for these collaterals, so please do not expect a functionality bug fix. These are used purely for PNR workshops and trainings

  Language:Verilog2310

• ZipCPU/zipcpu

  A small, light weight, RISC CPU soft core

  Language:Verilog1.2k152

• ZipCPU/wb2axip

  Bus bridges and other odds and ends

  Language:Verilog45595

• pulp-platform/pulp

  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

  Language:SystemVerilog431115

• pulp-platform/axi

  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  Language:SystemVerilog985244

• XUANTIE-RV/opene902

  OpenXuantie - OpenE902 Core

  Language:Verilog12760

• plctlab/RISCV-Training

  Training Materials for RISC-V HW/SW, focusing on compilers, emulators, and virtual machines. provided by PLCT Lab.

  318

• cnrv/home

  为推广RISC-V尽些薄力

  Language:SCSS29959

• hailiang-wang/nnetcpp

  Simple, Fast and Powerful RNN for textsum

  Language:C++1

• Varuzhan97/Vanilla-Recurrent-Neural-Network

  Vanilla RNN to perform a simple sentiment analysis task.

  Language:C++2

• rilesdg3/caffe2-Tutorial

  Creates a simple net and an rnn using Caffe2 cpp

  Language:C++82

• xuehy/toy-RNN

  A simple implementation of Naive RNN

  Language:C++51

• TheThirdOne/elf-edit

  Simple hex editor with highlighting for ELF binaries

  Language:Rust529

• TheThirdOne/rars

  RARS -- RISC-V Assembler and Runtime Simulator

  Language:Java1.1k217

• krocki/dnc

  Simple RNN, LSTM and Differentiable Neural Computer in pure Numpy

  Language:Python410122

• Trinkle23897/Artificial-Neural-Network-THU-2018

  4 small homeworks

  Language:Python4011

• dhm2013724/yolov2_xilinx_fpga

  A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard

  Language:C739229

• jlpteaching/dinocpu

  A teaching-focused RISC-V CPU design used at UC Davis

  Language:Scala13538

• cxlisme/FPGA-proj

  FPGA project

  Language:VHDL18344

• anupam-io/ES203-COA-CNN

  ES-203 Computer Organization & Architecture CNN on FPGA board

  Language:Verilog78

• MasLiang/CNN-On-FPGA

  FPGA

  Language:Verilog13434