WWeiying

ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

ccf-deadlines

⏰ Collaboratively track deadlines of conferences recommended by CCF (Website, Python Cli, Wechat Applet) / If you find it useful, please star this project, thanks~

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Computer-Science-Lectures-Peripheral

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

gem5

This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews should be submitted to https://gem5-review.googlesource.com/. The mirrors are synchronized every 15 minutes.

llvm-project

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.

riscv-dv

Random instruction generator for RISC-V processor verification

riscv-gnu-toolchain

GNU toolchain for RISC-V, including GCC

riscv-isa-sim

Spike, a RISC-V ISA Simulator

WWeiying/ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

WWeiying/ccf-deadlines

⏰ Collaboratively track deadlines of conferences recommended by CCF (Website, Python Cli, Wechat Applet) / If you find it useful, please star this project, thanks~

WWeiying/chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

WWeiying/Computer-Science-Lectures-Peripheral

WWeiying/cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

WWeiying/gem5

This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews should be submitted to https://gem5-review.googlesource.com/. The mirrors are synchronized every 15 minutes.

WWeiying/llvm-project

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.

WWeiying/riscv-dv

Random instruction generator for RISC-V processor verification

WWeiying/riscv-gnu-toolchain

GNU toolchain for RISC-V, including GCC

WWeiying/riscv-isa-sim

Spike, a RISC-V ISA Simulator

WWeiying/hwacha

Microarchitecture implementation of the decoupled vector-fetch accelerator

WWeiying/monica

DIY Watch based on ESP32-S3 and Amoled screen

WWeiying/riscv-boom

SonicBOOM: The Berkeley Out-of-Order Machine

WWeiying/riscv-fast-interrupt

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)

WWeiying/riscv-opcodes

RISC-V Opcodes

WWeiying/riscv-pk

RISC-V Proxy Kernel

WWeiying/riscv-tools

RISC-V Tools (ISA Simulator and Tests)

WWeiying/rocket-chip

Rocket Chip Generator

WWeiying/sail-riscv

Sail RISC-V model

WWeiying/SRT-4-DIVISION

RADIX-4 SRT division

WWeiying/wweiying.github.io