Pinned Repositories
missing-semester
The Missing Semester of Your CS Education 📚
AHB-Lite-Protocol-Project
cvw
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
dotfiles
Dotfiles
Gitpractice
Gittask3
missing-semester
The Missing Semester of Your CS Education 📚
su21-lab-starter
Verilog
This GitHub repository hosts a collection of straightforward Verilog examples and compact mini projects. These resources serve as a practical reference for learning Verilog programming and exploring its application in small-scale projects.
WaseemEng
Config files for my GitHub profile.
WaseemEng's Repositories
WaseemEng/AHB-Lite-Protocol-Project
WaseemEng/cvw
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
WaseemEng/dotfiles
Dotfiles
WaseemEng/Gitpractice
WaseemEng/Gittask3
WaseemEng/missing-semester
The Missing Semester of Your CS Education 📚
WaseemEng/su21-lab-starter
WaseemEng/Verilog
This GitHub repository hosts a collection of straightforward Verilog examples and compact mini projects. These resources serve as a practical reference for learning Verilog programming and exploring its application in small-scale projects.
WaseemEng/WaseemEng
Config files for my GitHub profile.