WazaAbdulkadir

I am a digital design engineer at YongaTek Microelectronics company

Pinned Repositories

APB-Protocol-Project-
APB master with two slaves read and write operation
Language:SystemVerilog0 1 00
caravel_first
0 1 02
Debounce
Language:Verilog00
Direct-Mapped-Cache
Language:Verilog00
gupsiseAkademi
Language:Verilog00
image_decode
Language:Python00
image_encode
Language:MATLAB00
Pierian-Data-Complete-Python-3-Bootcamp
Language:Jupyter Notebook0 0 00
Processor_that_can_communicate_with_UART
A simple processor that have ability to communicate with ysing UART
Language:SystemVerilog40
PWM
Language:Verilog1 1 00

WazaAbdulkadir's Repositories

WazaAbdulkadir/Processor_that_can_communicate_with_UART
A simple processor that have ability to communicate with ysing UART
Language:SystemVerilog40
WazaAbdulkadir/PWM
Language:Verilog1 1 00
WazaAbdulkadir/APB-Protocol-Project-
APB master with two slaves read and write operation
Language:SystemVerilog0 1 00
WazaAbdulkadir/caravel_first
0 1 02
WazaAbdulkadir/Debounce
Language:Verilog00
WazaAbdulkadir/Direct-Mapped-Cache
Language:Verilog00
WazaAbdulkadir/gupsiseAkademi
Language:Verilog00
WazaAbdulkadir/image_decode
Language:Python00
WazaAbdulkadir/image_encode
Language:MATLAB00
WazaAbdulkadir/Pierian-Data-Complete-Python-3-Bootcamp
Language:Jupyter Notebook0 0 00
WazaAbdulkadir/python_projects
Language:Python1 0