WeikangQiao

Pinned Repositories

AutoBridge
[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
Language:C++00
AutoSA
AutoSA: Polyhedral-Based Systolic Array Compiler
Language:C++0 0 00
CDSC
00
Deflate-HLS
Language:C++0 1 01
fio
Flexible I/O Tester
Language:C0 0 00
fpga-zynq
Support for Rocket Chip on Zynq FPGAs
Language:Tcl00
HT-Deflate-FPGA
0 2 00
icse2020-artifacts
Artifacts submission for ICSE 2020: HeteroRefactor
Language:C++0 0 00
Insider
Insider system.
Language:Tcl01
TopSort
Language:SystemVerilog24

WeikangQiao's Repositories

WeikangQiao/TopSort
Language:SystemVerilog24
WeikangQiao/AutoBridge
[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
Language:C++00
WeikangQiao/AutoSA
AutoSA: Polyhedral-Based Systolic Array Compiler
Language:C++0 0 00
WeikangQiao/CDSC
00
WeikangQiao/Deflate-HLS
Language:C++0 1 01
WeikangQiao/fio
Flexible I/O Tester
Language:C0 0 00
WeikangQiao/fpga-zynq
Support for Rocket Chip on Zynq FPGAs
Language:Tcl00
WeikangQiao/HT-Deflate-FPGA
0 2 00
WeikangQiao/icse2020-artifacts
Artifacts submission for ICSE 2020: HeteroRefactor
Language:C++0 0 00
WeikangQiao/Insider
Insider system.
Language:Tcl01
WeikangQiao/lib-deflate
Heavily optimized library for DEFLATE/zlib/gzip compression and decompression
Language:C
WeikangQiao/ma_hls
repository for HLS files from Master Thesis
Language:C++
WeikangQiao/research_helpers
Language:Verilog
WeikangQiao/SDAccel_Examples
SDAccel Examples
Language:C++1 0
WeikangQiao/SMEM_Fully_Pipelined_Design
SMEM++, A Fully Pipelined and Time-Multiplexed SMEM Seeding Accelerator for Genome Sequencing
Language:Verilog
WeikangQiao/ThesisCode
Code for my thesis project.
Language:C++1 0
WeikangQiao/Vitis_Accel_Examples
Vitis_Accel_Examples
WeikangQiao/vivado-library
Language:VHDL
WeikangQiao/ZYBO
Language:C