UMJI-VE370 Project
Model both single cycle and pipelined implementation of MIPS computer in Verilog that support a subset of MIPS instruction set including:
- The memory-reference instructions load word (lw) and store word (sw)
- The arithmetic-logical instructions add, addi, sub, and, andi, or, and slt
- The jumping instructions branch equal (beq), branch not equal (bne), and jump (j)