Wren6991

Interests: C, Verilog, Python Dislikes: C, Verilog, Python

Cambridge, UK

Pinned Repositories

asciiwave
Turn WaveDrom timing diagrams into ASCII art
Language:Python134 9 18
DVI-PMOD
DVI PMOD adapter (HDMI connector)
27 5 05
Hazard3
3-stage RV32IMACZb* processor with debug
Language:Verilog71 8 58
libfpga
Reusable Verilog 2005 components for FPGA designs
Language:Verilog25 5 03
NorForkConditionally
What's the simplest CPU you can build?
Language:C++30 8 00
Pico-DVI-Sock
A DVI Sock board for Pico
170 15 225
PicoDVI
Bitbanged DVI on the RP2040 Microcontroller
Language:C1.1k 47 49118
PicoStation3D
3D games console based on RP2040 and iCE40 UP5k
Language:C42 7 16
RISCBoy
Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink
Language:C227 18 310
Ship-Sandbox
Sinking ship simulation written in C++
Language:C++80 12 432

Wren6991's Repositories

Wren6991/PicoDVI
Bitbanged DVI on the RP2040 Microcontroller
Language:C1.1k 47 49118
Wren6991/RISCBoy
Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink
Language:C227 18 310
Wren6991/asciiwave
Turn WaveDrom timing diagrams into ASCII art
Language:Python134 9 18
Wren6991/Hazard3
3-stage RV32IMACZb* processor with debug
Language:Verilog71 8 58
Wren6991/libfpga
Reusable Verilog 2005 components for FPGA designs
Language:Verilog25 5 03
Wren6991/SmolDVI
Low-area DVI experiment for iCE40 UP5k and HX1k FPGAs
Language:Verilog22 4 03
Wren6991/ChristmasSoC
Dual-core RISC-V SoC with JTAG, atomics, SDRAM
Language:Verilog21 4 02
Wren6991/Hazard2
Smol 2-stage RISC-V processor in nMigen
Language:Python21 6 01
Wren6991/OpenDAP
Language:C++19 4 01
Wren6991/TwoWireDebug
Yet Another Debug Transport
Language:Verilog18 5 0
Wren6991/Hazard5
5-stage RISC-V CPU, originally developed for RISCBoy
Language:Verilog11 5 01
Wren6991/tt02-whisk-serial-processor
Whisk: 16-bit serial processor for TT02
Language:Verilog11 1 0
Wren6991/Bico
Dual-RP2040 development board with built-in debug
6 1 0
Wren6991/fpgascripts
Loose collection of scripts for FPGA work
Language:Python5 3 02
Wren6991/picosystem-experiments
Language:C3 3 0
Wren6991/riscv-formal
RISC-V Formal Verification Framework
Language:Verilog3 3 0
Wren6991/rvcpp
Language:C++3 2 0
Wren6991/virtual-jtag-dtm
Language:C3 2 0
Wren6991/49er
Minimal Python text editor using curses
Language:Python1 2 0
Wren6991/ecp5_jtag
Use ECP5 JTAG port to interact with user design
Language:Verilog1 2 0
Wren6991/gambatte-core
Fork of https://github.com/sinamas/gambatte with Pokemon speedrunning-related changes.
Language:Assembly1 2 0
Wren6991/Hazard3-SWD-SoC
Example Hazard3 + OpenDAP RISC-V SWD SoC integration
Language:Verilog1 2 0
Wren6991/riscv-isa-manual
RISC-V Instruction Set Manual
Language:TeX1 2 0
Wren6991/riscv-tests
Language:C1 2 0
Wren6991/buildroot
Buildroot, making embedded Linux easy. Note that this is not the official repository, but only a mirror. The official Git repository is at http://git.buildroot.net/buildroot/. Do not open issues or file pull requests here.
Language:Makefile1 0
Wren6991/embench-iot
The main Embench repository
Language:C2 0
Wren6991/Hazard1
Minimal RV32I processor with register file in RAM
Language:Verilog1 0
Wren6991/opensbi
RISC-V Open Source Supervisor Binary Interface
Language:C0 0
Wren6991/riscv-arch-test
Language:Assembly1 0
Wren6991/riscv-test-env
Language:C0 0