XiakaiPan/terosHDL

The goal of TerosHDL is make the FPGA development easier and reliable. It is a powerful open source IDE.

TerosHDL

Teros Technology: http://www.terostech.com/

Our philosophy is: think in hardware, develop hardware, take advantage of software tools.

The goal of TerosHDL is make the FPGA development easier and reliable. It is a powerful open source IDE.

Currently we support:

• Ghdl.
• ModelSim.
• Vhdl
• VUnit.

Soon we will support Verilog and others simulators.

Dependencies

• Symbolator: https://kevinpt.github.io/symbolator/#installation
• Git
• TerosHDLbackend >= 0.1.1: pip install TerosHDL
• VUnit: pip install vunit_hdl

For simulation:

• Ghdl/Modelsim

For code coverage:

• Ghdl with GCC backend.
• LCOV

For waveform:

• GTKWave/ModelSim

Installation

apm install terosHDL

Getting started guide

Runing test

Code coverage

Creating component diagram

Structure view

State machine diagram

This is an experimental feature. Not all state machines are supported.

User Manual

You have a complete user manual.

License

Copyright (c) 2018-Present

• Carlos Alberto Ruiz Naranjo, carlosruiznaranjo@gmail.com
• Ismael Pérez Rojo, ismaelprojo@gmail.com

TerosHDL is licensed under GPLv3.