Xilinx/PYNQ_Composable_Pipeline

Investigate if max_slots in `switch.py` are set correctly

Closed this issue · 2 comments

self.max_slots = int(description['parameters']['C_NUM_MI_SLOTS'])

+1 should be added to the line above.

With an hwh file generated from Vivado 2022.1, the C_NUM_MI_SLOTS reflects the actual number of ports in the switch and not the highest manager port index

This is not a bug. The code has also been modified to use NUM_MI 521fcb4