xilinx
There are 614 repositories under xilinx topic.
open-sdr/openwifi
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
LeiWang1999/FPGA
帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目
pConst/basic_verilog
Must-have verilog systemverilog modules
Xilinx/brevitas
Brevitas: neural network quantization in PyTorch
trabucayre/openFPGALoader
Universal utility for programming FPGA
hdl-util/hdmi
Send video/audio over HDMI on an FPGA
ultraembedded/biriscv
32-bit Superscalar RISC-V CPU
eugene-tarassov/vivado-risc-v
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
f4pga/prjxray
Documenting the Xilinx 7-series bit-stream format.
Cr4sh/s6_pcie_microblaze
PCI Express DIY hacking toolkit for Xilinx SP605. This repository is also home of Hyper-V Backdoor and Boot Backdoor, check readme for links and info
open-sdr/openwifi-hw
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
olofk/edalize
An abstraction library for interfacing EDA tools
trivialmips/nontrivial-mips
NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
VLSI-EDA/PoC
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
Xilinx/Vitis_Accel_Examples
Vitis_Accel_Examples
ZipCPU/wb2axip
Bus bridges and other odds and ends
bperez77/xilinx_axidma
A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.
f32c/f32c
A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz
jofrfu/tinyTPU
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
Xilinx/SDAccel_Examples
SDAccel Examples
WangXuan95/Xilinx-FPGA-PCIe-XDMA-Tutorial
Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核
pavel-demin/red-pitaya-notes
Notes on the Red Pitaya Open Source Instrument
Xilinx/CHaiDNN
HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs
definelicht/hlslib
A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
lastweek/fpga_readings
Recipe for FPGA cooking
Xilinx/RapidWright
Build Customized FPGA Implementations for Vivado
tymonx/logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
suoto/hdl_checker
Repurposing existing HDL tools to help writing better code
fpgasystems/Vitis_with_100Gbps_TCP-IP
100 Gbps TCP/IP stack for Vitis shells
MeowLucian/SDR_Matlab_OFDM_802.11a
:satellite: Using Software Designed Radio to transmit OFDM QPSK signals at 5 GHz
Xtra-Computing/ThunderGP
HLS-based Graph Processing Framework on FPGAs
Xilinx/xup_vitis_network_example
VNx: Vitis Network Examples
19801201/SpinalHDL_CNN_Accelerator
CNN accelerator implemented with Spinal HDL
UCLA-VAST/AutoBridge
[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
z4yx/petalinux-docker
Dockerfile to build docker images with Petalinux (Tested on version 2018.3~2021.1)
cea-wind/SimpleTPU
A FPGA Based CNN accelerator, following Google's TPU V1.