Pinned issues
Issues
- 5
- 10
- 3
- 7
- 8
Build problem for U50
#104 opened by danwetzel - 12
Is it possible to connect one QSFP port to second QSFP port of same board (alveo U250) instead of 2 alveo cards?
#85 opened by Sarika124 - 3
Can the XUP vitis network design work with 10G/25G Ethernet IP instead of the existing 100GEthernet IP ?
#123 opened by lizajoseph - 4
Compiling issue during routing phase with U250
#124 opened by GiacomoLevrini - 8
- 15
Does host_xrt supports U50?
#70 opened by sergey-gra - 6
Compiler error with Alveo xilinx_u50_gen3x16_xdma_5_202210_1 with Vivado and Vitis Version 2023.1 and XRT xrt_202310.2.15.225_20.04-amd64-xrt
#121 opened by lizajoseph - 4
Can a 10G or 25G NIC card be used to execute and implement this design with Alveo u50 card?
#120 opened by lizajoseph - 1
Implement 100G TCP/IP Offload Engine on U250
#119 opened by HirunaVishwamith - 0
How to set UDP MTU size and the UDP size in VNx?
#116 opened by liubenyuan - 1
Need ping before UDP transactions
#115 opened by liubenyuan - 3
Nolink when porting to ADM-PCIE-9V3
#114 opened by liubenyuan - 7
Bug reported: name `ol` is not defined.
#108 opened by zhangchenqi123 - 1
In branch `host_xrt`, the tx end can send the packets but the rx end keeps waiting.
#109 opened by zhangchenqi123 - 2
Exception: 'RuntimeError("There is no current event loop in thread \'Dask-Default-Threads-67128-0\'.")'
#107 opened by zhangchenqi123 - 1
About xilinx_u280_xdma_201920_3
#106 opened by pengjintao - 3
- 2
How to see the GUI of cmac_kernel in VIVADO ?
#102 opened by zhuofanzhang - 7
Alveo U50 stat_rx_status always 192
#90 opened by victornvq2 - 2
Reducing CMAC/NetworkLayer Frequency
#101 opened by ChunshuWu - 2
- 2
- 2
CMAC long bring-up time after xbutil reset
#98 opened by TheFlux7 - 9
Running vnx-basic notebook with an FPGA and a 100Gb NIC in different hosts
#93 opened by pouya-haghi - 7
Ping not working in "basic" design
#94 opened by pouya-haghi - 3
- 1
- 1
Alveo U25 compatibility
#89 opened by erenkal - 8
Payload size limitation [XRT]
#87 opened by KoalaYuFeng - 2
Failed to generate bitstream after passing synthesis and implementation [Vivado 2021.1, Alveo U250]
#84 opened by charles-typ - 13
Query: (1) why throughput higher than theoretical, (2) why lower throughput with 128B payload.
#81 opened by 108anup - 1
- 11
Version error
#64 opened by Qiang-Flute - 4
Does this repository support QDMA?
#80 opened by byeongkeonLee - 2
Netlayer customization
#78 opened by byeongkeonLee - 4
- 4
mm2s works only once, and limited
#76 opened by byeongkeonLee - 2
Socket table incorrect
#75 opened by trashcrash - 20
'xrt_core::error' what(): No IP matching 'cmac_0': Invalid argument while running 'basic' design through C++ host code
#71 opened by SPala121 - 3
VNx basic: number of sockets in hardware = 0
#73 opened by trashcrash - 7
- 2
Cannot assign slave segment '/interface_settings_0/S_AXI/reg0' into address space '/S_AXIL_nl' at address '0x0000_0000 [ 4K ]'
#69 opened by SPala121 - 9
Improve build time
#67 opened by victornvq30 - 9
- 4
VLNV Warning
#66 opened by victornvq30 - 3
Is it possible to use VNx example for connecting two cards on the same host?
#63 opened by sergey-gra