open-sdr/openwifi-hw

Issues

• May I ask which licenses Vivado needs besides Xilinx Viterbi Decoder license, because the Bitstream and HDF files we often compile cannot be used, thank you

  #62 opened 2 years ago by zhuzhineng
  1

• Generate Bitstream error:module 'module 'system' not found [system_wrapper.v:269]

  #54 opened 2 years ago by brealin
  6

• Bitstream Generation Problem

  #59 opened 2 years ago by chubohao
  5

• the synthesis (Run synthesis) stage fails.

  #107 opened 12 days ago by chenmo234
  0

• Generate Bitstream error : Generation of the IP CORE failed, Cannot upgrade to invalid target

  #106 opened 12 days ago by chenmo234
  1

• Vivado - critical warning

  #101 opened 5 months ago by remydemy
  2

• Compiling of FPGA-image failed for "zed_fmcs2-board"

  #102 opened 3 months ago by SteffenFri
  4

• 焦博士你好，我想问一下关于openofdm_tx模块的dot11_tx.v中，关于BCC模块的reset机制问题。

  #105 opened 3 months ago by wjq110
  0

• Simulation of ofdm Tx in FPGA

  #104 opened 4 months ago by hyanki
  0

• Issues Identified in OpenWiFi Scripts for Mesh Functionality

  #103 opened 4 months ago by Maxelectronics
  0

• Questions about tx_intf

  #99 opened 5 months ago by jonasxia
  1

• Modify the rate or modulation mode of tx

  #100 opened 5 months ago by Xiana1
  1

• ofdm direct-to-receive simulation and psdu modification

  #97 opened a year ago by fynkggwy5176
  0

• antsdr e310v2 pull request

  #96 opened a year ago by JiaoXianjun
  4

• Couldn't find the openofdm_tx_pre_def.v file for openofdm_tx verilog files.

  #92 opened a year ago by mliuvanteon
  0

• PCF mode

  #94 opened a year ago by huaxueyong
  1

• Hello,Dr.jiao. I have a question about the contention window of the csma code. I know that the traditional backoff window CWmin for CSMA/CA is 16, but the random number generation section in the csma_ca code starts from 2. How is this section defined? Or that I misunderstand the meaning of the source code?

  #90 opened a year ago by liulangkk
  4

• question

  #89 opened a year ago by huaxueyong
  12

• Couldn't find the Ubuntu 18/20/22 LTS release on the Ubuntu download website.

  #91 opened a year ago by mliuvanteon
  1

• no openwifi ssid WARNING: Tx Quadrature Calibration failed

  #88 opened a year ago by puzhitech
  0

• porting open-wifi to ad9375

  #73 opened a year ago by andrew712
  1

• rssi issue

  #84 opened a year ago by guessaname
  2

• openwifi compatible with vivado 2021 ML edition

  #86 opened a year ago by sdrlab
  6

• Problem with Vivado 2021.1 webpack, xc7z045ffg900-2 not supported

  #53 opened 2 years ago by catkira
  13

• Extracting samples after CFO correction

  #60 opened a year ago by Aaron3219
  3

• Question on the retransmission

  #83 opened 2 years ago by guessaname
  5

• some questions about "phase_offset" in module sync_short

  #82 opened 2 years ago by wwy9931154
  2

• How to expand the data bit width of Side_Info from 64bit to 128bit?

  #68 opened 2 years ago by KrisYuFi
  2

• fail to build bitstream for zc702+fmcs4

  #71 opened 2 years ago by hitanvil
  1

• Support for PlutoSDR

  #58 opened 2 years ago by catkira
  7

• source ./ip_repo_gen.tcl will report error

  #56 opened 2 years ago by cjhonlyone
  2

• dma_data of tx_intf not connected

  #57 opened 2 years ago by catkira
  2

• tx lo divider control register

  #55 opened 2 years ago by xiaogang05
  2

• hello, where is the top module (rx_intf, xpu, tx_intf）in FPGA, I can not find it. Than you!

  #50 opened 2 years ago by cg904699855
  1

• Simulation of 'openofdm_tx' and 'openofdm_rx'.

  #47 opened 3 years ago by kirateys
  11

• Advise on verifying the direct TX/RX wireless path.

  #45 opened 3 years ago by kirateys
  9

• Advise on connecting to the board.

  #44 opened 3 years ago by kirateys
  2

• Add ILAs to the HW-Design

  #39 opened 3 years ago by kirateys
  10

• ERROR: [Common 17-54] The object 'project' does not have a property 'legacy_ip_repo_paths'.

  #37 opened 3 years ago by kirateys
  6

• 802.11af Implementation for TVWS

  #38 opened 3 years ago by eshikafe
  1

• build open-wifi

  #36 opened 3 years ago by andrew712
  3

• Cannot build adrv9361z7035 board FPGA

  #35 opened 3 years ago by kelvin820
  4

• after Updating latest FPGA bitstream openwifi get fail to initiation

  #34 opened 3 years ago by kelvin820
  9

• how to use applications in Xilinx SDK?

  #33 opened 3 years ago by 18845725896peng
  1

• run openwifi.tcl

  #32 opened 3 years ago by 18845725896peng
  1

• TSF Time synchronization

  #31 opened 3 years ago by 18845725896peng
  1

• combine with the 802.1AS

  #30 opened 3 years ago by 18845725896peng
  2

• system module

  #26 opened 3 years ago by fatihilig-fpga
  6

• Data format of IQ

  #18 opened 4 years ago by hyanki
  13

• Problems when simulating openofdm_rx

  #17 opened 4 years ago by frestuc
  7