verilog
There are 4909 repositories under verilog topic.
logisim-evolution/logisim-evolution
Digital logic design tool and simulator
LeiWang1999/FPGA
帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目
chipsalliance/chisel
Chisel: A Modern Hardware Design Language
open-sdr/openwifi
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
verilator/verilator
Verilator open-source SystemVerilog simulator and lint system
SpinalHDL/VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
SI-RISCV/e200_opensource
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
darklife/darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
The-OpenROAD-Project/OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
jbush001/NyuziProcessor
GPGPU microprocessor architecture
cocotb/cocotb
cocotb: Python-based chip (RTL) verification
SpinalHDL/SpinalHDL
Scala based HDL
pConst/basic_verilog
Must-have verilog systemverilog modules
FPGAwars/icestudio
:snowflake: Visual editor for open FPGA boards
analogdevicesinc/hdl
HDL libraries and projects
olofk/serv
SERV - The SErial RISC-V CPU
riscv-mcu/e203_hbirdv2
The Ultra-Low Power RISC-V Core
The-OpenROAD-Project/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
ultraembedded/riscv
RISC-V CPU Core (RV32IM)
clash-lang/clash-compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
ZipCPU/zipcpu
A small, light weight, RISC CPU soft core
google/xls
XLS: Accelerated HW Synthesis
olofk/fusesoc
Package manager and build abstraction tool for FPGA/ASIC development
platformio/platformio-vscode-ide
PlatformIO IDE for VSCode: The next generation integrated development environment for IoT
chili-chips-ba/wireguard-fpga
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!
verilog-to-routing/vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
aappleby/metroboy
A repository of gate-level simulators and tools for the original Game Boy.
ultraembedded/biriscv
32-bit Superscalar RISC-V CPU
hughperkins/VeriGPU
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
siliconcompiler/siliconcompiler
Modular hardware build system
drom/awesome-hdl
Hardware Description Languages
circuitvalley/USB_C_Industrial_Camera_FPGA_USB3
Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.
splinedrive/kianRiscV
RISC-V XV6/Linux SoC, marchID: 0x2b
syntacore/scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
FPGAwars/apio
:seedling: Open source ecosystem for open FPGA boards
MikePopoloski/slang
SystemVerilog compiler and language services