verilog-to-routing/vtr-verilog-to-routing

Issues

• fix for ISO warning

  #2818 opened 10 days ago by heshpdx
  1

• Wire lookahead runtime scales poorly with number of switch/segment types

  #2811 opened 15 days ago by petergrossmann21
  4

• System Verilog support is broken due to compilation error in F4PGA plugin

  #2821 opened 9 days ago by MohamedElgammal
  0

• Update benchmark page descriptions for VTR 9 release

  #2810 opened 15 days ago by vaughnbetz
  0

• SDC Parsing causes assertion error for specific netlist sweeping option combination

  #2809 opened 16 days ago by petergrossmann21
  0

• `vtr_reg_nightly_test7/titan_other_run_flat` Failed

  #2786 opened 19 days ago by ueqri
  1

• [Placement] Inconsistency in Grid Blocks Data Structure

  #2801 opened 19 days ago by AlexandreSinger
  0

• Troubleshooting RR graphs with poor router performance

  #2803 opened 23 days ago by petergrossmann21
  4

• [Prepacker] Pack Molecule Data Structure Clarity

  #2791 opened a month ago by AlexandreSinger
  0

• NoC Congestion optimization options are not listed in the VTR docs

  #2788 opened a month ago by vaughnbetz
  2

• Comparing performance/quality trade-off of SPEC and VTR random number generators.

  #2798 opened a month ago by soheilshahrouz
  0

• VPR Test `test_odd_even_routing` Failed

  #2753 opened a month ago by ueqri
  4

• VTR format checking / auto-format not checked by CI?

  #2677 opened 4 months ago by vaughnbetz
  2

• Change in path from input to output place file causes digest error.

  #2783 opened a month ago by petergrossmann21
  0

• Optimize run time and memory footprint to build the choke point data structures in routing

  #2782 opened a month ago by vaughnbetz
  0

• Extend XY_SPECIFIED syntax support to fixed layout XML files

  #2767 opened a month ago by petergrossmann21
  12

• [Routing] Incremental Slack Timing Analysis Does Not Match When Computed From Scratch

  #2754 opened a month ago by AlexandreSinger
  5

• Update VTR quick start guide to use yosys / parmys

  #2739 opened a month ago by vaughnbetz
  6

• Issue with Molecule Clustering Causing Suboptimal Placement

  #2775 opened a month ago by WindFrank
  0

• Unexpected High Gain Causes Unrelated Blocks to Be Added to Clusters

  #2763 opened 2 months ago by WindFrank
  0

• Packing Devices from Two Separate Parts of a Netlist into a Single CLB

  #2726 opened 2 months ago by WindFrank
  1

• VPR error when trying to compile my design generated using PRGA

  #2760 opened 2 months ago by polarbearsrock
  0

• [IntraClusterPlacement] Code Cleanups

  #2732 opened 2 months ago by AlexandreSinger
  2

• Turn on choke point analysis in the router by default, and make help etc. more user-friendly

  #2750 opened 2 months ago by vaughnbetz
  2

• [TestScript] Enhance the Robustness of the VTR Flow Log Parser Script

  #2743 opened 2 months ago by ueqri
  0

• Overly Verbose Router Look ahead warnings

  #2748 opened 2 months ago by ZohairZaidi
  0

• vtr optional documentation showing up at the top of vtr::vector and vtr::vector_map documentation

  #2679 opened 2 months ago by vaughnbetz
  6

• Add visualization for flat routing in the VPR graphics

  #2740 opened 2 months ago by vaughnbetz
  1

• [Packer] Load The ClusteredNetlist Directly From The ClusterLegalizer

  #2731 opened 2 months ago by AlexandreSinger
  0

• [ClusterLegalizer] Code Cleanups

  #2730 opened 2 months ago by AlexandreSinger
  0

• [Packer] Setting Higher Target Pin Utilization When Regions are Full

  #2729 opened 2 months ago by AlexandreSinger
  0

• [Netlist] Potential Issue When Re-Creating Elements in Atom and Clustered Netlists

  #2690 opened 2 months ago by AlexandreSinger
  2

• [Logging] Overly Verbose Log Messages When Building RRGraph

  #2689 opened 2 months ago by AlexandreSinger
  3

• CLBs Positioned Far from IOs

  #2727 opened 2 months ago by WindFrank
  0

• [Build] VTR Fails to Build on ASSERT_LEVEL=4

  #2705 opened 2 months ago by AlexandreSinger
  2

• Improve 3D switch block commenting and move command line option to arch file

  #2722 opened 3 months ago by vaughnbetz
  0

• [IPA] MVP to manually test vpr --server mode

  #2704 opened 3 months ago by w0lek
  3

• VTR seems to struggle with being smart about how it packs into memories

  #2718 opened 3 months ago by WhiteNinjaZ
  0

• Multibit Adder Architecture Failure

  #2717 opened 3 months ago by shrekliao
  0

• (Caused by io location changed)The suspicious detour phenomenon that significantly reduces the slack

  #2716 opened 3 months ago by WindFrank
  0

• VTR throws warning for shorted SB connections

  #2712 opened 3 months ago by WhiteNinjaZ
  0

• Issue with Multibit Adder in VTR flagship architecture

  #2710 opened 3 months ago by shrekliao
  0

• [Logging] Incorrect LUT Sizes Circuit Statistic Printing

  #2685 opened 3 months ago by AlexandreSinger
  0

• ./kernel/yosys.h:42:10: fatal error: 'map' file not found

  #2697 opened 3 months ago by Martoni
  3

• Placement Constraints not working

  #2684 opened 3 months ago by GopalN
  8

• 3D switch block updates & commenting

  #2694 opened 3 months ago by vaughnbetz
  0

• if VPR have routing constraint like Xilinx fixed routing

  #2693 opened 3 months ago by teddyisgood
  0

• redundant adders when synthesizing addition with full adders

  #2681 opened 4 months ago by Junius00
  2

• Make a short coding style guide in the VTR developer guide

  #2678 opened 4 months ago by vaughnbetz
  0

• VPR warning verbosity with timing analysis on and custom routing graphs with isolated clock routing

  #2665 opened 4 months ago by petergrossmann21
  0