Verilog to Routing

Pinned Repositories

ezgl
Language:C++10 6 37
libblifparse
Parsing library for BLIF netlists
Language:C++19 4 211
libsdcparse
Language:C++12 5 27
tatum
Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits
Language:C++62 8 311
verilog-to-routing.github.io
Website for Verilog to Routing
Language:SCSS6 6 03
vtr-buildbot
Buildbot Infrastructure for VTR
Language:HTML6 21 05
vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Language:C++1.2k 62 1.1k430

Verilog to Routing's Repositories

verilog-to-routing/vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Language:C++1.2k 62 1.1k430
verilog-to-routing/tatum
Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits
Language:C++62 8 311
verilog-to-routing/libblifparse
Parsing library for BLIF netlists
Language:C++19 4 211
verilog-to-routing/libsdcparse
Language:C++12 5 27
verilog-to-routing/ezgl
Language:C++10 6 37
verilog-to-routing/verilog-to-routing.github.io
Website for Verilog to Routing
Language:SCSS6 6 03
verilog-to-routing/vtr-buildbot
Buildbot Infrastructure for VTR
Language:HTML6 21 05