SpinalHDL/VexRiscv

Issues

• Inquiry on running Dhrystone benchmark flow on VexRiscv

  #445 opened 7 days ago by nerdylye
  3

• Running Regression Test using post_synthesis verilog file

  #440 opened 8 days ago by nerdylye
  5

• Partitioning On-Chip RAM in Murax SoC and Mapping IP Access

  #443 opened a month ago by xavier-design
  3

• Any way to replace 'Area' with 'Component' in plugin's implementation?

  #441 opened 2 months ago by davine47
  5

• How to add extra memory to proessor

  #439 opened 2 months ago by karegoud
  5

• custom FPU

  #438 opened 2 months ago by ztachip
  1

• Regarding the regression test...

  #437 opened 2 months ago by nerdylye
  4

• Do you have plan to add FPU area timing option for vexriscv like vexii?

  #436 opened 2 months ago by littlezpf666
  2

• Verilog code integration with Murax SOC

  #435 opened 3 months ago by xavier-design
  0

• Exit cycle accurate simulation

  #398 opened 4 months ago by ashuthosh-mr
  1

• compiling CFU demo configurations results in : java.lang.Exception: Missing inserts : LEGAL_INSTRUCTION"

  #430 opened 6 months ago by jahagirdar
  1

• Verilator expects `-std=c++14`

  #431 opened 5 months ago by goekce
  1

• SiFive GCC link in Readme.md is dead.

  #429 opened 6 months ago by jahagirdar
  1

• What tools are supported

  #428 opened 6 months ago by SeanGan233
  2

• Instruction that need Multiple cycles for execution

  #424 opened 6 months ago by karegoud
  3

• DBusSimplePlugin's Wishbone support forces 32-bit reads

  #426 opened 6 months ago by kivikakk
  3

• Multiple register read from Register file

  #422 opened 6 months ago by xavier-design
  3

• Data buffer

  #419 opened 7 months ago by xavier-design
  6

• GenFullWithOfficialRiscvDebug failed

  #421 opened 7 months ago by Logiase
  1

• VexRiscv for custom processing in memory instructions

  #420 opened 7 months ago by neha2351
  2

• new custom instruction in vexriscv

  #418 opened 7 months ago by Chaitanya-kumar-Y
  11

• Help for custom instruction

  #411 opened 8 months ago by ztachip
  7

• how to send data serially using apbbus when using murax soc

  #414 opened 8 months ago by karegoud
  4

• machineCsr test failing

  #416 opened 8 months ago by jbrown11111
  2

• Internal timer implementation

  #415 opened 8 months ago by juliaazziz
  1

• Wrong speculative execution when conditional branch argument is in TCM address range

  #412 opened 9 months ago by vianney
  1

• rdcycle and rdinstret instructions not working

  #408 opened 9 months ago by MrJake222
  2

• default bus doesn't expose write mask

  #409 opened 9 months ago by MrJake222
  0

• VexRiscV shift bus fail

  #407 opened 9 months ago by MrJake222
  3

• EmbeddedRiscvJtag synthesis issue

  #381 opened 10 months ago by gregdavill
  7

• AxiCrossBar with Standard Axi4 Interface in Briey

  #406 opened 10 months ago by ic-hjx
  15

• How to use printf function?

  #402 opened 10 months ago by Guochen-Shine
  10

• Problem about how to compile the software that can be used in Vexriscv with FPU

  #401 opened a year ago by ic-hjx
  10

• How to only modify certain one reset kind of specific Reg in vex core.

  #405 opened a year ago by littlezpf666
  0

• How to only modify certain one reset kind of specific Reg in vex core.

  #404 opened a year ago by littlezpf666
  1

• About the Csr registers in Vexriscv

  #403 opened a year ago by ic-hjx
  2

• Problems with adding FPU in Briey

  #400 opened a year ago by Guochen-Shine
  5

• Instructions to save/restore register to stack is taking 2 clock each

  #387 opened a year ago by ztachip
  12

• Compile C code and run bare metal cycle accurate simulation

  #395 opened a year ago by nachiket
  3

• Debug instructions executed twice

  #396 opened a year ago by patstew
  5

• EU Funding

  #393 opened a year ago by PythonLinks
  3

• FPU plugin to GenFull.scala

  #392 opened a year ago by ashuthosh-mr
  3

• Data Stream in/out SoC <-> FPGA

  #391 opened a year ago by lk-davidegironi
  6

• Adding VexRiscV as a dependency

  #390 opened a year ago by DanielMadmon
  2

• DE0-Nano Board with VexRiscV: IO and Fit Design Issues Including Specific Command Used

  #389 opened a year ago by Tahamermer
  3

• Murax XIP compile issue

  #380 opened a year ago by lk-davidegironi
  11

• Fetch dosen't performed correctly in the simulation of Murax SOC.(+Custom instructions are executed in unexpected time.)

  #385 opened a year ago by nohahanon
  1

• Regarding the result of dhrystone with TCM

  #383 opened a year ago by piondeno
  6

• debug

  #384 opened a year ago by chshux
  1

• CPU exception signal

  #382 opened a year ago by snowprogrammer
  3