SpinalHDL

A high level hardware description language

Pinned Repositories

NaxRiscv
Language:Scala258 25 11139
SaxonSoc
SoC based on VexRiscv and ICE40 UP5K
Language:Scala147 23 3140
Spinal-bootcamp
SpinalHDL-tutorial based on Jupyter Notebook
Language:Jupyter Notebook40 5 07
SpinalDoc-RTD
The sources of the online SpinalHDL doc
Language:Python23 11 5760
SpinalHDL
Scala based HDL
Language:Scala1.6k 80 725317
SpinalTemplateSbt
A basic SpinalHDL project
Language:Scala75 9 2363
SpinalWorkshop
Labs to learn SpinalHDL
Language:Scala136 10 1840
VexiiRiscv
Like VexRiscv, but, Harder, Better, Faster, Stronger
Language:Scala95 12 2110
VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
Language:Assembly2.4k 101 333411
VexRiscvSoftcoreContest2018
Language:Verilog63 12 216

SpinalHDL's Repositories

SpinalHDL/VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
Language:Assembly2.4k 101 333411
SpinalHDL/SpinalHDL
Scala based HDL
Language:Scala1.6k 80 725317
SpinalHDL/NaxRiscv
Language:Scala258 25 11139
SpinalHDL/SaxonSoc
SoC based on VexRiscv and ICE40 UP5K
Language:Scala147 23 3140
SpinalHDL/SpinalWorkshop
Labs to learn SpinalHDL
Language:Scala136 10 1840
SpinalHDL/VexiiRiscv
Like VexRiscv, but, Harder, Better, Faster, Stronger
Language:Scala95 12 2110
SpinalHDL/SpinalTemplateSbt
A basic SpinalHDL project
Language:Scala75 9 2363
SpinalHDL/SpinalCrypto
SpinalHDL - Cryptography libraries
Language:Scala47 13 519
SpinalHDL/openocd_riscv
Spen's Official OpenOCD Mirror
Language:C45 6 2233
SpinalHDL/Spinal-bootcamp
SpinalHDL-tutorial based on Jupyter Notebook
Language:Jupyter Notebook40 5 07
SpinalHDL/SpinalDoc
SpinalHDL documentation assets (pictures, slides, ...)
Language:HTML31 13 913
SpinalHDL/VexRiscvSocSoftware
Language:C24 8 315
SpinalHDL/SpinalDoc-RTD
The sources of the online SpinalHDL doc
Language:Python23 11 5760
SpinalHDL/CocotbLib
Language:Python15 9 27
SpinalHDL/rvls
RISCV lock-step checker based on Spike
Language:C++8 5 0
SpinalHDL/NaxSoftware
Language:C7 9 15
SpinalHDL/docker
Language:Dockerfile4 8 07
SpinalHDL/SpinalTemplateSbtDependencies
An SpinalHDL project example which use VexRiscv git as a dependency
Language:Scala4 5 01
SpinalHDL/SpinalNomad
Language:Dockerfile3 8 1
SpinalHDL/SpinalTemplateGradle
A basic SpinalHDL project, configured with Gradle instead of SBT
Language:Scala3 3 11
SpinalHDL/NaxRiscv-Rtd
Language:Python2 6 03
SpinalHDL/buildroot-spinal-saxon
Language:C1 5 06
SpinalHDL/riscv-compliance
Language:Assembly1 6 0
SpinalHDL/riscv-isa-sim
Spike, a RISC-V ISA Simulator
Language:C1 2 01
SpinalHDL/VexiiRiscv-RTD
Language:Python1 5 01
SpinalHDL/buildroot
Buildroot, making embedded Linux easy. Note that this is not the official repository, but only a mirror. The official Git repository is at http://git.buildroot.net/buildroot/. Do not open issues or file pull requests here.
Language:Makefile7 04
SpinalHDL/coremark
CoreMark® is an industry-standard benchmark that measures the performance of central processing units (CPU) and embedded microcrontrollers (MCU).
Language:C7 0
SpinalHDL/embench-iot
The main Embench repository
Language:C2 01
SpinalHDL/linux
Language:C7 01
SpinalHDL/naxriscv_doc
1 0