SpinalHDL

A high level hardware description language

Pinned Repositories

NaxRiscv
Language:Scala268 25 11540
SaxonSoc
SoC based on VexRiscv and ICE40 UP5K
Language:Scala151 23 3140
Spinal-bootcamp
SpinalHDL-tutorial based on Jupyter Notebook
Language:Jupyter Notebook43 5 07
SpinalDoc-RTD
The sources of the online SpinalHDL doc
Language:Python25 11 6061
SpinalHDL
Scala based HDL
Language:Scala1.7k 81 753336
SpinalTemplateSbt
A basic SpinalHDL project
Language:Scala78 9 2365
SpinalWorkshop
Labs to learn SpinalHDL
Language:Scala145 11 1839
VexiiRiscv
Like VexRiscv, but, Harder, Better, Faster, Stronger
Language:Scala113 12 2513
VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
Language:Assembly2.5k 102 334421
VexRiscvSoftcoreContest2018
Language:Verilog63 12 216

SpinalHDL's Repositories

SpinalHDL/VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
Language:Assembly2.5k 102 334421
SpinalHDL/SpinalHDL
Scala based HDL
Language:Scala1.7k 81 753336
SpinalHDL/NaxRiscv
Language:Scala268 25 11540
SpinalHDL/SaxonSoc
SoC based on VexRiscv and ICE40 UP5K
Language:Scala151 23 3140
SpinalHDL/SpinalWorkshop
Labs to learn SpinalHDL
Language:Scala145 11 1839
SpinalHDL/VexiiRiscv
Like VexRiscv, but, Harder, Better, Faster, Stronger
Language:Scala113 12 2513
SpinalHDL/SpinalTemplateSbt
A basic SpinalHDL project
Language:Scala78 9 2365
SpinalHDL/SpinalCrypto
SpinalHDL - Cryptography libraries
Language:Scala50 14 519
SpinalHDL/openocd_riscv
Spen's Official OpenOCD Mirror
Language:C48 6 2234
SpinalHDL/Spinal-bootcamp
SpinalHDL-tutorial based on Jupyter Notebook
Language:Jupyter Notebook43 5 07
SpinalHDL/SpinalDoc
SpinalHDL documentation assets (pictures, slides, ...)
Language:HTML32 13 913
SpinalHDL/VexRiscvSocSoftware
Language:C26 8 315
SpinalHDL/SpinalDoc-RTD
The sources of the online SpinalHDL doc
Language:Python25 11 6061
SpinalHDL/CocotbLib
Language:Python15 9 27
SpinalHDL/rvls
RISCV lock-step checker based on Spike
Language:C++10 6 01
SpinalHDL/NaxSoftware
Language:C8 10 15
SpinalHDL/docker
Language:Dockerfile4 8 07
SpinalHDL/SpinalSchemaGen
Language:Scala41
SpinalHDL/SpinalTemplateGradle
A basic SpinalHDL project, configured with Gradle instead of SBT
Language:Scala4 3 12
SpinalHDL/SpinalTemplateSbtDependencies
An SpinalHDL project example which use VexRiscv git as a dependency
Language:Scala4 5 01
SpinalHDL/NaxRiscv-Rtd
Language:Python2 6 03
SpinalHDL/buildroot-spinal-saxon
Language:C1 5 06
SpinalHDL/riscv-compliance
Language:Assembly1 6 0
SpinalHDL/riscv-isa-sim
Spike, a RISC-V ISA Simulator
Language:C1 2 02
SpinalHDL/VexiiRiscv-RTD
Language:Python1 5 03
SpinalHDL/coremark
CoreMark® is an industry-standard benchmark that measures the performance of central processing units (CPU) and embedded microcrontrollers (MCU).
Language:C7 0
SpinalHDL/embench-iot
The main Embench repository
Language:C2 01
SpinalHDL/linux
Language:C7 01
SpinalHDL/naxriscv_doc
1 0
SpinalHDL/VexiiFirmware
Language:C