SpinalHDL

A high level hardware description language

Pinned Repositories

NaxRiscv
Language:Scala269 25 11540
SaxonSoc
SoC based on VexRiscv and ICE40 UP5K
Language:Scala151 23 3140
Spinal-bootcamp
SpinalHDL-tutorial based on Jupyter Notebook
Language:Jupyter Notebook43 5 07
SpinalDoc-RTD
The sources of the online SpinalHDL doc
Language:Python26 11 6061
SpinalHDL
Scala based HDL
Language:Scala1.7k 81 755337
SpinalTemplateSbt
A basic SpinalHDL project
Language:Scala78 9 2365
SpinalWorkshop
Labs to learn SpinalHDL
Language:Scala145 11 1840
VexiiRiscv
Like VexRiscv, but, Harder, Better, Faster, Stronger
Language:Scala118 12 2613
VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
Language:Assembly2.5k 102 337423
VexRiscvSoftcoreContest2018
Language:Verilog63 12 216

SpinalHDL's Repositories

SpinalHDL/VexRiscvSoftcoreContest2018
Language:Verilog63 12 216
SpinalHDL/SpinalBaseProject-OLD-
Language:Scala10 7 05
SpinalHDL/riscv-formal
RISC-V Formal Verification Framework
Language:Verilog5 6 0
SpinalHDL/sd_device
SD device emulator from ProjectVault
Language:Verilog3 2 01
SpinalHDL/opensbi
RISC-V Open Source Supervisor Binary Interface
Language:C1 2 04
SpinalHDL/SpinalTemplateMill
A simple SpinalHDL demo project based on Mill
Language:Scala1 2 01
SpinalHDL/VexRiscvRegressionData
Used to store heavy data required to run full VexRiscv regressions
Language:Assembly1 7 08
SpinalHDL/cocotb
Coroutine Co-simulation Test Bench
Language:Python5 01
SpinalHDL/u-boot
"Das U-Boot" Source Tree
Language:C3 14
SpinalHDL/zephyr
Primary GIT Repository for the Zephyr Project
Language:C7 01