SpinalHDL/NaxRiscv

Issues

• storeFresh unused : trap-store_access_fault

  #111 opened a month ago by Bill94l
  5

• About performance evaluation

  #124 opened 2 months ago by yyyjjp
  1

• Is there any implementation of FENCE instructions?

  #123 opened 2 months ago by zyn810039594
  2

• about litex and dhrystone

  #96 opened 7 months ago by duanjiulon
  41

• Question about the sizes of cache L2 & L1

  #109 opened 3 months ago by phillippZZ
  7

• about the gen.scala and ifetch

  #119 opened 4 months ago by duanjiulon
  18

• Performance counter CSR registers that are not implemented are seen as implemented

  #121 opened 4 months ago by Bill94l
  2

• How to run a bare metal program with mulitple cpus

  #122 opened 4 months ago by phillippZZ
  0

• The check of the register Rd/Rs is not equal to zero is missing for some compressed instructions

  #114 opened 4 months ago by Bill94l
  2

• Nax not trap on store fault

  #116 opened 4 months ago by atkarim
  5

• Need help with the infrastructure regarding interconnection

  #118 opened 4 months ago by phillippZZ
  6

• cache_throttling && dirty evicts counting.

  #87 opened 5 months ago by SoCScholar
  10

• WFI instruction

  #112 opened 5 months ago by Bill94l
  11

• How to integrate my own IP

  #113 opened 5 months ago by phillippZZ
  3

• A trap is triggered when the pmpcfg register is read by csrr

  #110 opened 5 months ago by Bill94l
  8

• RVLS and testsGen.py

  #70 opened 5 months ago by Bill94l
  6

• The mmu_sv39.elf fail with SocSim

  #88 opened 5 months ago by Bill94l
  18

• cache WB (Writeback) counter increment when reading cache line and D refill counter when writing into cache line

  #75 opened 5 months ago by SoCScholar
  26

• Drawing the cache architecture

  #76 opened 5 months ago by SoCScholar
  1

• Non blocking cache

  #97 opened 5 months ago by SoCScholar
  6

• L1 cache communication with CPU core

  #94 opened 5 months ago by SoCScholar
  0

• Memfilter and interface/Tilelink channel communicating with L2 cache and Memfilter

  #93 opened 5 months ago by SoCScholar
  0

• How to customize hardware architecture

  #102 opened 6 months ago by phillippZZ
  15

• Read data incorrectly when executing `c.lwsp` instruction

  #104 opened 6 months ago by zhangkanqi
  9

• Accessing addr 0x0000001e doesn't throw access fault exception

  #108 opened 6 months ago by zhangkanqi
  3

• Does NaxRiscv update mtval after trap illegal_inst?

  #107 opened 6 months ago by zhangkanqi
  2

• NaxRiscv sets sepc[0]=1 which is against the riscv privileged spec

  #101 opened 6 months ago by zhangkanqi
  3

• Wrong value of `sie` after trapping store_access_fault

  #105 opened 6 months ago by zhangkanqi
  1

• Does NaxRicv support S-mode?

  #103 opened 6 months ago by zhangkanqi
  12

• [Bug Report] Executing `sfence.vma` under U-mode doesn't throw illegal inst exception

  #106 opened 6 months ago by zhangkanqi
  0

• An exception arose when reading instructions from the ELF file

  #99 opened 6 months ago by zhangkanqi
  15

• NaxRiscv gets the wrong value when reading from `scause`

  #100 opened 6 months ago by zhangkanqi
  4

• Problems about debug and Halt the Nax

  #98 opened 6 months ago by xie-1399
  8

• how to run a nax_core with a AXI4 interface

  #81 opened 9 months ago by duanjiulon
  13

• Hi,can you privide an example?

  #82 opened 7 months ago by duanjiulon
  56

• Some guidance on better timing

  #89 opened 8 months ago by tristanitschner
  3

• Request for Guidance: Starting with a Minimal Framework

  #71 opened a year ago by skylayer
  4

• Error in implementation of SRAW and SRAIW instructions

  #95 opened 7 months ago by Nanotrust
  3

• Changing Naxriscv instructions - command

  #92 opened 8 months ago by mdmriscv
  1

• L1/L2 cache and integration with CPU pipeline

  #91 opened 8 months ago by SoCScholar
  2

• Read a sram that is changed by other host

  #90 opened 8 months ago by zyn810039594
  1

• LINUX on Litex_NaxRISCV ( Linux-capable, RISC-V-based SoC )

  #86 opened 8 months ago by SoCScholar
  17

• Wrong mask for 64 bits IO access in NaxRiscvProbe

  #84 opened 9 months ago by Bill94l
  1

• riscv tests with virtual memory enabled fail

  #83 opened 9 months ago by Bill94l
  3

• [BUG] CSR write verification error in the Verilator wrapper

  #78 opened 10 months ago by Bill94l
  5

• Default branch direction prediction should be TAKEN (currently NOT TAKEN)

  #79 opened 10 months ago by ronan-lashermes
  1

• ext/NaxSoftware/init.sh not up-to-date

  #77 opened 10 months ago by Bill94l
  1

• NaxRiscv running custom test cases prompts FAILURE ???

  #72 opened a year ago by LMiaoH
  9

• Loop when change GShare RAM

  #73 opened 10 months ago by zyn810039594
  2

• Mark framebuffer as non-cacheable

  #74 opened a year ago by egorxe
  5