Issues
- 7
Question about the sizes of cache L2 & L1
#109 opened by phillippZZ - 18
about the gen.scala and ifetch
#119 opened by duanjiulon - 2
Performance counter CSR registers that are not implemented are seen as implemented
#121 opened by Bill94l - 0
How to run a bare metal program with mulitple cpus
#122 opened by phillippZZ - 2
The check of the register Rd/Rs is not equal to zero is missing for some compressed instructions
#114 opened by Bill94l - 5
Nax not trap on store fault
#116 opened by atkarim - 6
- 10
cache_throttling && dirty evicts counting.
#87 opened by SoCScholar - 11
WFI instruction
#112 opened by Bill94l - 5
storeFresh unused : trap-store_access_fault
#111 opened by Bill94l - 3
How to integrate my own IP
#113 opened by phillippZZ - 8
- 6
RVLS and testsGen.py
#70 opened by Bill94l - 18
The mmu_sv39.elf fail with SocSim
#88 opened by Bill94l - 26
cache WB (Writeback) counter increment when reading cache line and D refill counter when writing into cache line
#75 opened by SoCScholar - 1
Drawing the cache architecture
#76 opened by SoCScholar - 6
Non blocking cache
#97 opened by SoCScholar - 0
L1 cache communication with CPU core
#94 opened by SoCScholar - 0
Memfilter and interface/Tilelink channel communicating with L2 cache and Memfilter
#93 opened by SoCScholar - 37
about litex and dhrystone
#96 opened by duanjiulon - 15
How to customize hardware architecture
#102 opened by phillippZZ - 9
- 3
- 2
- 3
- 1
- 12
Does NaxRicv support S-mode?
#103 opened by zhangkanqi - 0
[Bug Report] Executing `sfence.vma` under U-mode doesn't throw illegal inst exception
#106 opened by zhangkanqi - 15
- 4
- 8
Problems about debug and Halt the Nax
#98 opened by xie-1399 - 13
how to run a nax_core with a AXI4 interface
#81 opened by duanjiulon - 56
Hi,can you privide an example?
#82 opened by duanjiulon - 3
Some guidance on better timing
#89 opened by tristanitschner - 4
- 3
- 1
Changing Naxriscv instructions - command
#92 opened by mdmriscv - 2
L1/L2 cache and integration with CPU pipeline
#91 opened by SoCScholar - 1
Read a sram that is changed by other host
#90 opened by zyn810039594 - 17
- 1
Wrong mask for 64 bits IO access in NaxRiscvProbe
#84 opened by Bill94l - 3
riscv tests with virtual memory enabled fail
#83 opened by Bill94l - 5
- 1
Default branch direction prediction should be TAKEN (currently NOT TAKEN)
#79 opened by ronan-lashermes - 1
ext/NaxSoftware/init.sh not up-to-date
#77 opened by Bill94l - 9
- 2
Loop when change GShare RAM
#73 opened by zyn810039594 - 5
Mark framebuffer as non-cacheable
#74 opened by egorxe - 25
- 11
64 bit risc v core from tilelink/socSim.scala.
#68 opened by SoCScholar