Read data incorrectly when executing `c.lwsp` instruction

[zhangkanqi]

Hi,
there is an mismatch between NaxRiscv and Spike when reading from addr 0x80002018 using c.lwsp instruction.

*** INTEGER WRITE DATA PC=80000388 DUT=40 REF=ffffffff8519e9ca ***

I have no idea why this will happen. Could you please help me with this mismatch?

For Debug: input_27.zip

For Reproduce:
NaxRiscv: f335738

cd $NAXRISCV
vim NaxRiscv/src/main/scala/naxriscv/Gen.scala # enable Rvc&float&double in Gen64
sbt "runMain naxriscv.Gen64"
cd $NAXRISCV/src/test/cpp/naxriscv
make clean; make compile
./obj_dir/VNaxRiscv --load-elf=./input_nax_27.elf --start-symbol=_start --pass-symbol=write_tohost --timeout=100000 --name=input_nax_0 --trace --trace-ref --spike-debug

[Dolu1990]

Got it fixed, the issue was core 0: 0x0000000080000b92 (0xe00d9053) fclass.s zero, fs11

The FPU interface was still writing the register file, while it shouldn't (because zero)

Thanks :)

By the way, are you using some fuzzing / random code generator tool to find those bugs ?

[zhangkanqi]

I see. Thanks a lot.
Yes, I found these bug via an undisclosed fuzzer.

[Dolu1990]

Note, i'm working since november on VexiiRiscv :
https://github.com/SpinalHDL/VexiiRiscv

It is in order, but support dual-issue + late ALU. It can already run multicore debian on hardware.
Let's me know if you are interrested fusing it ^^. Like NaxRiscv, its simulation run in lockstep against spike (through rvls)
I can help with the setup.

[zhangkanqi]

Of course! It's my pleasure.
Actually I'm doing research on cpu fuzzing(RTL Level). I'll try to test VexiiRiscv when I'm not busy. Can you provide setup steps in VexiiRiscv, like https://github.com/SpinalHDL/NaxRiscv/blob/main/src/test/cpp/naxriscv/README.md.

By the way, are NaxRiscv, VexRiscv and VexiiRiscv all written in SpinalHDL? How can I translate SpinalHDL to FIRRTL, and FIRRTL to
Verilog step by step?

[Dolu1990]

Here is the current documentation to run VexiiRiscv simulation :
https://spinalhdl.github.io/VexiiRiscv-RTD/master/VexiiRiscv/HowToUse/index.html

Note it is based on SpinalSim (itself use verilator under the hood)

Running things using Test/runMain vexiiriscv.tester.TestBench is kinda slow because of the warmup time, that's why i would say to instead use :
Test/runMain vexiiriscv.tester.TestBenchServer

This will create a simulation server which can then run new simulation very very fast.
To run a new simulation on it you just need to send a command via telnet, for instance :
echo '--load-elf xxx.elf --name miaou' | nc localhost 8189

By the way, are NaxRiscv, VexRiscv and VexiiRiscv all written in SpinalHDL?

Yes it is all SpinalHDL stuff.

How can I translate SpinalHDL to FIRRTL, and FIRRTL to Verilog step by step?

SpinalHDL isn't using FIRRTL. SpinalHDL "AST" can be modified by the user directly while you generate the CPU itself. It is in some way more integrated than Chisel/FIRRTL.
So it depend what you want to do ?

[Dolu1990]

Hoo also, note that VexiiRiscv by default is configured with a very slime configuration. RV32I

[zhangkanqi]

Thank you for your patient reply, I will try it later.

SpinalHDL isn't using FIRRTL. SpinalHDL "AST" can be modified by the user directly while you generate the CPU itself. It is in some way more integrated than Chisel/FIRRTL.

Actually, I want to do some instrumentations to collect runtime information of NaxRiscv in FIRRTL representation. In detail, I can analysis the circuit(described by FIRRTL) and add some FIRRTL statements to the circuit automatically during the process of FIRRTL convert to verilog.
So I wonder can I instrument SpinalHDL "AST like FIRRTL? If so, can you provide some help of how to instrument?

[Dolu1990]

So I wonder can I instrument SpinalHDL "AST like FIRRTL?

From my understanding of what you mean, yes you can. But it is done directly at SpinalHDL time itself, not through a generated intermediate file.

There is some documentation here :
https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Developers%20area/spinalhdl_datamodel.html

Also note that because NaxRiscv is made of plugins, you could even add new plugins to instrument it without having to touch the ast the "hard" way

[zhangkanqi]

This looks like what I really want.
Thanks a lot!