Does NaxRicv support S-mode?

Hi,
I wonder know does NaxRicv support S-mode, or where can I find the support of S-mode in NaxRiscv?
Thanks.

Hi,

Yes it does (it is required to run linux)
It is enabled by default (

NaxRiscv/src/main/scala/naxriscv/Gen.scala

Line 50 in f335738

withSupervisor : Boolean = true,

)

You mean that if I don't run Linux, S-mode is not supported?

NaxRiscv throws an illegal instruction exception when it encounters sret instruction without running Linux.

You mean that if I don't run Linux, S-mode is not supported?

Running linux and s-mode are 2 different things

To execute sret, you need to be in supervisor mode i think. Were you in supervisor mode ?

It seems executing sret under M-mode? (But Spike doesn't throw any exception at sret.)
Here is the debug log in Spike:

I just checked the nax source code, sret under machine should be ok.

Can you send me the waveform / how you generate nax / verilog ?

No Problem!
Here are all files for debugging you will need: input_3.zip
For reproduce:
NaxRiscv: f335738

cd $NAXRISCV
vim NaxRiscv/src/main/scala/naxriscv/Gen.scala # enable Rvc&float&double in Gen64
sbt "runMain naxriscv.Gen64"
cd $NAXRISCV/src/test/cpp/naxriscv
./obj_dir/VNaxRiscv --load-elf=./input_nax_3.elf --start-symbol=_start --pass-symbol=write_tohost --timeout=100000 --name=input_nax_0 --trace --trace-ref --spike-debug

Thanks, it should be fixed now :)

Witht the elf you sent me, it later trigger a scause missmatch, but it is due to the software writing 0x1f in scause, which is too much bits

Yes. We have discussed in #100.
Thanks for your confirmation.

However, whether an illegal inst exception should be thrown when an executing sret depends on mstatus.TSR. The descriptions in spec(version20240411) are as follows:

Your modification seems have no regard for mstatus.TSR? I'm not sure if your modification is correct because I'm not familiar with your code.

Should be good now, tsr, tw, tvm weren't implemented