riscv
There are 918 repositories under riscv topic.
Tencent/ncnn
ncnn is a high-performance neural network inference framework optimized for the mobile platform
mytechnotalent/Reverse-Engineering
A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.
unicorn-engine/unicorn
Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)
capstone-engine/capstone
Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86.
OAID/Tengine
Tengine is a lite, high performance, modular inference engine for embedded device
rcore-os/rCore
Rust version of THU uCore OS. Linux compatible.
misprit7/computerraria
A fully compliant RISC-V computer made inside the game Terraria
chipsalliance/rocket-chip
Rocket Chip Generator
SpinalHDL/VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
darklife/darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
earlephilhower/arduino-pico
Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards
limine-bootloader/limine
Modern, advanced, portable, multiprotocol bootloader and boot manager.
probe-rs/probe-rs
A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host
riscv-boom/riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
ucb-bar/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
sipeed/MaixPy-v1
MicroPython for K210 RISC-V, let's play with edge AI easier
stnolting/neorv32
:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
oreboot/oreboot
oreboot is a fork of coreboot, with C removed, written in Rust.
o8vm/octox
Unix-like OS in Rust inspired by xv6-riscv
riscv-mcu/e203_hbirdv2
The Ultra-Low Power RISC-V Core
TheThirdOne/rars
RARS -- RISC-V Assembler and Runtime Simulator
sysprog21/shecc
A self-hosting and educational C optimizing compiler
genodelabs/genode
Genode OS Framework
rustsbi/rustsbi
RISC-V Supervisor Binary Interface (RISC-V SBI) library in Rust; runs on M or HS mode; good support for embedded Rust ecosystem. For binary download see https://github.com/rustsbi/prototyper.
openhwgroup/cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
LekKit/RVVM
The RISC-V Virtual Machine
syntacore/scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
eugene-tarassov/vivado-risc-v
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
chipsalliance/Cores-VeeR-EH1
VeeR EH1 core
d0iasm/rvemu
RISC-V emulator for CLI and Web written in Rust with WebAssembly. It supports xv6 and Linux (ongoing).
Wren6991/Hazard3
3-stage RV32IMACZb* processor with debug
splinedrive/kianRiscV
RISC-V Linux SoC, marchID: 0x2b
eunomia-bpf/eunomia-bpf
A Toolchain to make Build and Run eBPF programs easier
michaeljclark/rv8
RISC-V simulator for x86-64
github0null/eide
An embedded development environment for mcs51/stm8/avr/cortex-m/riscv on VsCode.
takahirox/riscv-rust
RISC-V processor emulator written in Rust+WASM