openhwgroup/cv32e40p

Issues

• recipe for target 'testbench_verilator' failed (verilator Warning-COMBDLY) - when executing make in cv32e40p/sim/core/Makefile

  #1032 opened 2 months ago by Ribisl
  1

• Error during elaboration in xcelium

  #1021 opened 5 months ago by vasanth00
  2

• Instruction reencoding documentation

  #1031 opened 5 months ago by Guilherme-Soares-Sequeira
  3

• Existed version of cv32e40p pipeline graph

  #1030 opened 5 months ago by ahmdotm
  1

• RTL code coverage hole in CV32E40P lzc

  #1022 opened 5 months ago by YoannPruvost
  1

• RTL Code Coverage Hole in cv32e40p_EX_stage module line 237 and 241

  #1023 opened 5 months ago by YoannPruvost
  1

• CV32E40P_TRACE_EXECUTION

  #1028 opened 5 months ago by nimakolahi
  8

• Not used PULP DIV/SQRT still mentioned in User Manual v1.8.3

  #1027 opened 5 months ago by pascalgouedo
  0

• RTL Code Coverage Hole in fpnew_divsqrt_th_32 module line 287 and 288 for FPU configuration

  #1019 opened 6 months ago by YoannPruvost
  0

• Missing area metrics for ASIC synthesis

  #1002 opened 6 months ago by thomasdingemanse
  2

• RTL Code Coverage Hole in cv32e40p_EX_stage module line 396 for FPU configuration

  #1018 opened 6 months ago by YoannPruvost
  0

• RTL Code Coverage Hole in cv32e40p_EX_stage module line 387 for FPU configuration

  #1017 opened 6 months ago by YoannPruvost
  0

• RTL Code Coverage Hole in cv32e40p_EX_stage module line 211 for FPU configuration

  #1016 opened 6 months ago by YoannPruvost
  0

• RTL Code Coverage Hole in cv32e40p_ID_stage module line 872

  #1015 opened 6 months ago by YoannPruvost
  0

• RTL Code Coverage Hole in cv32e40p_controller module lines 1241

  #1012 opened 6 months ago by YoannPruvost
  0

• RTL Code Coverage Hole in cv32e40p_controller module lines 1187 and 1210

  #1011 opened 6 months ago by YoannPruvost
  0

• RTL Code Coverage Hole in cv32e40p_controller module line 850 and lines 852 to 887

  #1010 opened 6 months ago by pascalgouedo
  0

• RTL Code Coverage Hole in cv32e40p_controller module line 831

  #1009 opened 6 months ago by pascalgouedo
  0

• RTL Code Coverage Hole in cv32e40p_controller module line 675

  #1007 opened 6 months ago by pascalgouedo
  0

• RTL Code Coverage Hole in cv32e40p_controller module lines 632 and 642

  #1006 opened 6 months ago by pascalgouedo
  0

• RTL Code Coverage Hole in cv32e40p_controller module line 640

  #1005 opened 6 months ago by pascalgouedo
  0

• RTL Code Coverage Hole in cv32e40p_controller module line 399

  #1004 opened 6 months ago by pascalgouedo
  0

• CVFPU RTL updates for implementation tools

  #1001 opened 6 months ago by pascalgouedo
  2

• Combinational loops in synthesis (cv32e40px) when adding co-processor through CV-X-IF

  #1000 opened 6 months ago by gonzo-sal
  9

• Debug: Which version of OpenOCD

  #999 opened 6 months ago by CLappin
  3

• Floating Point Unit (FPU) not working

  #990 opened 7 months ago by zeshan-10xe
  1

• HWLoop count not updated when last instruction is a CSR access with pipeline flush

  #975 opened 8 months ago by pascalgouedo
  1

• Issue #722 correction introduced latches in combinatorial process

  #901 opened a year ago by pascalgouedo
  1

• Code coverage report

  #988 opened 7 months ago by bekbeis
  4

• Missing case default

  #959 opened 9 months ago by pascalgouedo
  1

• Impossible to cover case default

  #960 opened 8 months ago by pascalgouedo
  1

• FPU power consumption

  #965 opened 9 months ago by pascalgouedo
  1

• Branch predictor in cv32e40p core will take more time.

  #951 opened 10 months ago by Attaullah786
  8

• How can I build this core?

  #955 opened 8 months ago by Unlimitosu
  2

• Ensure Makefiles support both SNPS VCS and Siemens Questa for the above

  #982 opened 8 months ago by DBees
  1

• Clarification on cv.clipr signedness

  #967 opened 9 months ago by realqhc
  2

• cv32e40p implementation on Arty a7 100T FPGA

  #958 opened 9 months ago by Amal-k-Ayyan
  2

• Suggested update to the FPGA Synthesis sub-section of the User Manual

  #948 opened 9 months ago by MikeOpenHWGroup
  1

• cv32e40p_prefetch_buffer: Is it ok to assert hwlp_jump_i when there are no outstanding instr_ requests (ie cnt_q == 0)?

  #954 opened 10 months ago by bdiz
  4

• cv32e40p_obi_interface: When TRANS_STABLE=0, unstable transaction can still pass through to obi interface.

  #950 opened 10 months ago by bdiz
  4

• Error in Analysis and Synthesis in Quartus

  #943 opened 10 months ago by vidushiy25
  21

• Seeking Information on RTL Access

  #946 opened 10 months ago by arunvthampi
  8

• Incorporating FPU

  #947 opened 10 months ago by vidushiy25
  2

• Missing files

  #945 opened a year ago by Amal-k-Ayyan
  3

• HW Loop Constraints question

  #937 opened a year ago by jstraus59
  5

• Help needed: Integration of cvFPU with cv32e40p and adding a custom instruction

  #924 opened a year ago by diggi0330
  5

• What is "MPEC" that is mentioned in the documentation?

  #917 opened a year ago by jstraus59
  2

• Why aren't post-increment loads with RD==RS1 treated as illegal?

  #920 opened a year ago by Silabs-ArjanB
  6

• FLW, C_CLW, C_FLWSP instructions fail to change MSTATUS.FS to DIRTY state

  #896 opened a year ago by dd-baoshan
  1

• Hello world simulating optimization failed error

  #895 opened a year ago by vidushiy25
  4