MikeOpenHWGroup
Functional verification of RTL for ASICs and FPGAs. Sole Proprietor at Covrado and Director of Engineering, Verification Task Group at the OpenHW Group.
@openhwgroup Ottawa, Ontario, Canada
Pinned Repositories
core-v-cores
CORE-V Family of RISC-V Cores
core-v-isg
RISC-V Random Instruction Stream Generator
core-v-mcu-uvm
CORE-V MCU UVM Environment and Test Bench
core-v-xif
RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
cv32e40p-riscof
✔️Port of RISCOF to demonstrate the CV32E40P Processor's RISC-V ISA compatibility.
pulp_soc
riscv-dv
SV/UVM based instruction generator for RISC-V processor verification
core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
programs
Documentation for the OpenHW Group's set of CORE-V RISC-V cores
MikeOpenHWGroup's Repositories
MikeOpenHWGroup/cv32e40p-riscof
✔️Port of RISCOF to demonstrate the CV32E40P Processor's RISC-V ISA compatibility.
MikeOpenHWGroup/core-v-cores
CORE-V Family of RISC-V Cores
MikeOpenHWGroup/core-v-mcu-uvm
CORE-V MCU UVM Environment and Test Bench
MikeOpenHWGroup/core-v-xif
RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
MikeOpenHWGroup/cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
MikeOpenHWGroup/cv32e40s
4 stage, in-order, secure RISC-V core based on the CV32E40P
MikeOpenHWGroup/cv32e40x
4 stage, in-order, compute RISC-V core based on the CV32E40P
MikeOpenHWGroup/cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
MikeOpenHWGroup/siliconcompiler
SiliconCompiler is an open source compiler framework that automates translation from source code to silicon.
MikeOpenHWGroup/advanced-riscv-verification-methodologies
Advanced Verification Methodologies for RISC-V and related IP
MikeOpenHWGroup/bare-metal-programming-guide
A bare metal programming guide (ARM microcontrollers)
MikeOpenHWGroup/core-v-mcu
This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
MikeOpenHWGroup/core-v-mcu-cli-test
Eclipse/FreeRTOS/core-v-mcu example program
MikeOpenHWGroup/core-v-mcu-devkit
This is the CORE-V MCU DevKit project, hosting the open-source artifacts for the CORE-V MCU Development Kit.
MikeOpenHWGroup/core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
MikeOpenHWGroup/cv32e20-dv
MikeOpenHWGroup/cv32e40x-dv
CV32E40X Design-Verification environment
MikeOpenHWGroup/cva5-accelerators
MikeOpenHWGroup/cve2
Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
MikeOpenHWGroup/cvw
Configurable RISC-V Processor
MikeOpenHWGroup/DVplan_reviewer
Experimenting with DVplan reviews
MikeOpenHWGroup/egos-2000
A minimal operating system (2K LOC) on QEMU and a RISC-V board
MikeOpenHWGroup/experimental-repo
MikeOpenHWGroup/force-riscv
Instruction Set Generator initially contributed by Futurewei
MikeOpenHWGroup/marketing
MikeOpenHWGroup/programs
Documentation for the OpenHW Group's set of CORE-V RISC-V cores
MikeOpenHWGroup/really-awesome-opensource-asic-resources
MikeOpenHWGroup/riscv-profiles
RISC-V Architecture Profiles
MikeOpenHWGroup/verilog-ethernet
Verilog Ethernet components for FPGA implementation
MikeOpenHWGroup/x-heep
eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V