vidushiy25

Pinned Repositories

• core-v-verif

  Functional verification project for the CORE-V family of RISC-V cores.

  Language:Assembly42347501218

• cv32e40p

  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

  Language:SystemVerilog92481482410

• VexRiscv

  A FPGA friendly 32 bit RISC-V CPU implementation

  Language:Assembly2.4k101331407

vidushiy25's Repositories