Issues
- 0
make verilog error
#3703 opened by abendezu10 - 0
Error 1 build-setup.sh: Build script failed with exit code 2 at step 5: Pre-compiling Chipyard Scala sources
#3701 opened by sking-007 - 1
- 0
Spike and rocket's csr registers behave differently
#3697 opened by 90ICEDA - 3
RoCC Core Clock Gating Bug
#3695 opened by moniriki - 1
RoCC: io.mem.req.ready stuck
#3635 opened by ARF1939261764 - 2
- 4
Error when building the project
#3623 opened by iagrigorov - 1
Remove "master/slave" terminology from Rocket Chip repo
#3684 opened by ben-k - 2
- 4
- 0
Cannot find *behav_srams.v` in generated verilog files
#3686 opened by xlgforever - 0
- 2
Chisel generates invalid nesting of always blocks and/or initializations.
#3677 opened by leviathanch - 1
- 3
Creating 32 bit rocket-chip without fpu
#3669 opened by gituserdeepika - 4
- 3
Colliding module name: ALU
#3671 opened by leviathanch - 0
Issue in VTestDriver__Trace__2__Slow.cpp
#3672 opened by gituserdeepika - 6
- 4
Make verilog Error
#3657 opened by Krishnakumarmohanraj - 4
./build-setup.sh errors in chipyard flow
#3663 opened by gituserdeepika - 2
./build.sh not found and make verilog error
#3662 opened by gituserdeepika - 3
class RocketChip$macro$3 needs to be abstract.
#3646 opened by Amagicman - 3
Error in ./build.sh setp of rocket-tools
#3584 opened by MateusFauri - 0
- 9
[Proposal] Nextgen rocket-chip planning thread.
#3620 opened by lordspacehog - 0
vcs compile error
#3649 opened by dimory - 2
Bus Error Unit cannot find implicit clock when RocketTile crossingType is set to RationalCrossing
#3647 opened by Kevin99214 - 1
Error: Assertion failed: 'A' channel re-used a source ID when running simulation in QuestaSim
#3644 opened by thangngoECE - 1
- 12
Generation of verilog file for rocket chip
#3601 opened by srishti-sr - 1
MCAUSE register holds wrong exception
#3633 opened by bantierr - 1
Add support for desiredName overrides for ClockDomains
#3638 opened by bchetwynd - 0
Debugging section of README.md leads nowhere
#3636 opened by Nerotos - 2
Rocket updates sepc and stval in M mode
#3629 opened by zhangkanqi - 0
HART specific opearations at DRAM controller / adding hartid to memory requests
#3632 opened by FelixWagner00 - 2
Discrepency between simulation with and without traces
#3630 opened by bantierr - 1
- 1
Unable to make verilog
#3617 opened by ic-ssc - 1
Using make Config Generated Verilog with TestHarness in Vivado for Logic Synthesis
#3611 opened by fengmu0124 - 1
Mill resolve error
#3618 opened by srishti-sr - 1
Verilog generation
#3619 opened by srishti-sr - 2
Remove Scalar Crypto and BitManip?
#3609 opened by csgxiong - 1
parameter not find in freechips.rocketchip.config
#3603 opened by tangjiaping - 2
Bus error unit cannot be added, fails diplomacy
#3607 opened by Kevin99214 - 5
[Proposal] Refactor the remaining helpers out of the diplomacy module in rocket-chip.
#3604 opened by lordspacehog - 4
Split utils into independent repository?
#3596 opened by jerryz123 - 1
Code style, scalafix, and scalafmt discussion.
#3597 opened by lordspacehog - 0
Debugging with GCD Link broken
#3581 opened by sebastianornelas