Pinned Repositories
rocket-chip
Rocket Chip Generator
DRAMSim2
DRAMSim2: A cycle accurate DRAM simulator
hwacha-net
Hwacha Neural Network
onnx-halide
A Halide backend for ONNX
riscv-OpenBLAS
OpenBLAS is an optimized BLAS library based on GotoBLAS2 1.13 BSD version.
riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
riscv-isa-sim
Spike, a RISC-V ISA Simulator
chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
constellation
A Chisel RTL generator for network-on-chip interconnects
saturn-vectors
Chisel RISC-V Vector 1.0 Implementation
jerryz123's Repositories
jerryz123/onnx-halide
A Halide backend for ONNX
jerryz123/riscv-OpenBLAS
OpenBLAS is an optimized BLAS library based on GotoBLAS2 1.13 BSD version.
jerryz123/hwacha-net
Hwacha Neural Network
jerryz123/DRAMSim2
DRAMSim2: A cycle accurate DRAM simulator
jerryz123/rocket-chip
Rocket Chip Generator
jerryz123/Swan
Swan Benchmark Suite
jerryz123/ariane
Ariane is a 6-stage RISC-V CPU capable of booting Linux
jerryz123/block-inclusivecache-sifive
jerryz123/boom-template
A template for building new projects/platforms using the BOOM core.
jerryz123/chisel3
Chisel 3: A Modern Hardware Design Language
jerryz123/coremark-pro
Containing dozens of real-world and synthetic tests, CoreMark®-PRO (2015) is an industry-standard benchmark that measures the multi-processor performance of central processing units (CPU) and embedded microcrontrollers (MCU)
jerryz123/embench-iot
The main Embench repository
jerryz123/espresso
jerryz123/fa22tapeout-course-dev
jerryz123/firrtl
Flexible Intermediate Representation for RTL
jerryz123/gem5
This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews should be submitted to https://gem5-review.googlesource.com/. The mirrors are synchronized every 15 minutes.
jerryz123/git
Git Source Code Mirror - This is a publish-only repository and all pull requests are ignored. Please follow Documentation/SubmittingPatches procedure for any of your improvements.
jerryz123/Halide
a language for fast, portable data-parallel computation
jerryz123/onnx
Open Neural Network Exchange
jerryz123/onnx-composer
jerryz123/parsec
jerryz123/riscv-gnu-toolchain
GNU toolchain for RISC-V, including GCC
jerryz123/riscv-isa-manual
RISC-V Instruction Set Manual
jerryz123/riscv-isa-sim
Spike, a RISC-V ISA Simulator
jerryz123/riscv-pk
RISC-V Proxy Kernel
jerryz123/riscv-test-env
jerryz123/riscv-tests
jerryz123/riscv-vector-tests
The missing test suite for RISC-V V extension.
jerryz123/sifive-blocks
Common RTL blocks used in SiFive's projects
jerryz123/test-chipyard