chisel
There are 170 repositories under chisel topic.
OpenXiangShan/XiangShan
Open-source high-performance RISC-V processor
chipsalliance/chisel
Chisel: A Modern Hardware Design Language
chipsalliance/rocket-chip
Rocket Chip Generator
ucb-bar/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
riscv-boom/riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
ucb-bar/riscv-mini
Simple RISC-V 3-stage Pipeline in Chisel
RadicalCSG/Chisel.Prototype
Work in progress prototype for the Chisel Level Editor, for Unity
m3rcer/Chisel-Strike
A .NET XOR encrypted cobalt strike aggressor implementation for chisel to utilize faster proxy and advanced socks5 capabilities.
T-K-233/RISC-V-Single-Cycle-CPU
RISC-V 32bit single-cycle CPUs written in Logisim, Verilog, and Chisel
opiran-club/pf-tun
All-in-one OPIran scripts
Azumi67/Chisel_multipleServers
Establish a Reverse Tunnel between different servers and clients. IPV4 | IPV6 - Supports TCP & UDP . You can establish a tunnel between 5 Kharej servers & 1 IRAN server and vice versa.
raster-gpu/raster-i
A 3D FPGA GPU for real-time rasterization with a tile-based deferred rendering (TBDR) architecture, featuring transform & lighting (T&L), back-face culling, MSAA anti-aliasing, ordered dithering, etc.
ucb-bar/chiseltest
The batteries-included testing and formal verification library for Chisel-based RTL designs.
bu-icsg/dana
Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
ucb-bar/constellation
A Chisel RTL generator for network-on-chip interconnects
t3l3machus/pentest-pivoting
A compact guide to network pivoting for penetration testings / CTF challenges.
ucsc-vama/essent
high-performance RTL simulator
MaxXSoft/Fuxi
Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
im-tomu/fomu-workshop
Support files for participating in a Fomu workshop
chiselverify/chiselverify
A dynamic verification library for Chisel.
FyraLabs/chisel-operator
Kubernetes Operator for Chisel
loykylewong/FPGA-Application-Development-and-Simulation
《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).
maltanar/fpga-tidbits
Chisel components for FPGA projects
freechipsproject/diagrammer
Provides dot visualizations of chisel/firrtl circuits
ucb-bar/saturn-vectors
Chisel RISC-V Vector 1.0 Implementation
ovh/sv2chisel
(System)Verilog to Chisel translator
carlosedp/chiselv
A RISC-V Core (RV32I) written in Chisel HDL
RadicalCSG/com.chisel
Chisel CSG Level Editor, for Unity
Azumi67/Direct_Chisel
Establishing a Direct tunnel using chisel between Servers and Client - IPV4 | IPV6 - TCP | UDP - [5] Kharej [1] IRAN
sifive/chisel-circt
Library to compile Chisel circuits using LLVM/MLIR (CIRCT)
unblocked/chissl
A tool to create HTTPS reverse tunnels
rhysd/riscv32-cpu-chisel
Learning how to make RISC-V 32bit CPU with Chisel
IA-C-Lab-Fudan/Chisel-FFT-generator
FFT generator using Chisel
luoqisheng/lldb-symbolic
lldb命令-symbolic
sujinnaljin/Improving_Productivity
🛠 lldb, breakpoint, shortcut 등을 이용한 생산성 향상 방법을 배워보자 🛠
pku-liang/Sanger
A co-design architecture on sparse attention