chisel
There are 144 repositories under chisel topic.
OpenXiangShan/XiangShan
Open-source high-performance RISC-V processor
chipsalliance/chisel
Chisel: A Modern Hardware Design Language
chipsalliance/rocket-chip
Rocket Chip Generator
riscv-boom/riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
ucb-bar/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
ucb-bar/riscv-mini
Simple RISC-V 3-stage Pipeline in Chisel
RadicalCSG/Chisel.Prototype
Work in progress prototype for the Chisel Level Editor, for Unity
m3rcer/Chisel-Strike
A .NET XOR encrypted cobalt strike aggressor implementation for chisel to utilize faster proxy and advanced socks5 capabilities.
ucb-bar/chiseltest
The batteries-included testing and formal verification library for Chisel-based RTL designs.
Azumi67/Chisel_multipleServers
Establish a Reverse Tunnel between different servers and clients. IPV4 | IPV6 - Supports TCP & UDP . You can establish a tunnel between 5 Kharej servers & 1 IRAN server and vice versa.
bu-icsg/dana
Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
t3l3machus/pentest-pivoting
A compact guide to network pivoting for penetration testings / CTF challenges.
opiran-club/pf-tun
All-in-one OPIran scripts
im-tomu/fomu-workshop
Support files for participating in a Fomu workshop
MaxXSoft/Fuxi
Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
ucb-bar/constellation
A Chisel RTL generator for network-on-chip interconnects
chiselverify/chiselverify
A dynamic verification library for Chisel.
ucsc-vama/essent
high-performance RTL simulator
freechipsproject/diagrammer
Provides dot visualizations of chisel/firrtl circuits
maltanar/fpga-tidbits
Chisel components for FPGA projects
ovh/sv2chisel
(System)Verilog to Chisel translator
carlosedp/chiselv
A RISC-V Core (RV32I) written in Chisel HDL
Azumi67/Direct_Chisel
Establishing a Direct tunnel using chisel between Servers and Client - IPV4 | IPV6 - TCP | UDP - [5] Kharej [1] IRAN
sifive/chisel-circt
Library to compile Chisel circuits using LLVM/MLIR (CIRCT)
FyraLabs/chisel-operator
Kubernetes Operator for Chisel
luoqisheng/lldb-symbolic
lldb命令-symbolic
rhysd/riscv32-cpu-chisel
Learning how to make RISC-V 32bit CPU with Chisel
IA-C-Lab-Fudan/Chisel-FFT-generator
FFT generator using Chisel
sujinnaljin/Improving_Productivity
🛠 lldb, breakpoint, shortcut 등을 이용한 생산성 향상 방법을 배워보자 🛠
panda5mt/KyogenRV
The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
sergiovks/eCPPTv2-Personal-Cheatsheet-ESP-
Personal CheatSheet used for the exam made with Obsidian, download the repo and use the resources within Obsidian for a better experience. CHISEL & SOCAT BINARIES ARE WITHIN THE PIVOTING SECTION.
pku-liang/Sanger
A co-design architecture on sparse attention
microdynamics-cpu/tree-core-cpu
:deciduous_tree: A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.
grebe/ofdm
Chisel Things for OFDM
IBM/chiffre
A fault-injection framework using Chisel and FIRRTL
thoughtworks/hardposit-chisel3
Chisel library for Unum Type-III Posit Arithmetic