rtl

There are 1032 repositories under rtl topic.

  • youngsoft/MyLinearLayout

    MyLayout is a powerful iOS UI framework implemented by Objective-C. It integrates the functions with Android Layout,iOS AutoLayout,SizeClass, HTML CSS float and flexbox and bootstrap. So you can use LinearLayout,RelativeLayout,FrameLayout,TableLayout,FlowLayout,FloatLayout,PathLayout,GridLayout,LayoutSizeClass to build your App 自动布局 UIView UITableView UICollectionView RTL

    Language:Objective-C4.4k164142894
  • chisel

    chipsalliance/chisel

    Chisel: A Modern Hardware Design Language

    Language:Scala3.8k148999572

  • chipsalliance/rocket-chip

    Rocket Chip Generator

    Language:Scala3k1979451.1k

  • layoutBox/PinLayout

    Fast Swift Views layouting without auto layout. No magic, pure code, full control and blazing fast. Concise syntax, intuitive, readable & chainable. [iOS/macOS/tvOS/CALayer]

    Language:Swift2.3k44109142
  • verilator

    verilator/verilator

    Verilator open-source SystemVerilog simulator and lint system

    Language:C++2.2k743.3k542

  • darklife/darkriscv

    opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

    Language:Verilog1.9k8640270

  • MohammadYounes/rtlcss

    Framework for transforming Cascading Style Sheets (CSS) from Left-To-Right (LTR) to Right-To-Left (RTL)

    Language:JavaScript1.7k40206127

  • riscv-boom/riscv-boom

    SonicBOOM: The Berkeley Out-of-Order Machine

    Language:Scala1.6k84281405

  • SpinalHDL/SpinalHDL

    Scala based HDL

    Language:Scala1.5k78669301

  • ucb-bar/chipyard

    An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

    Language:Scala1.5k81627593
  • neorv32

    stnolting/neorv32

    :desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

    Language:VHDL1.5k48177201

  • The-OpenROAD-Project/OpenROAD

    OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

    Language:Verilog1.4k541.1k483

  • The-OpenROAD-Project/OpenLane

    OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

    Language:Python1.2k57940358

  • kartik-v/bootstrap-star-rating

    A simple yet powerful JQuery star rating plugin with fractional rating support.

    Language:JavaScript1k66178400

  • pulp-platform/axi

    AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

    Language:SystemVerilog94938117242

  • eldraco/Salamandra

    Salamandra is a tool to find spy microphones that use radio freq to transmit. It uses SDR.

    Language:Python816556116

  • syntacore/scr1

    SCR1 is a high-quality open-source RISC-V MCU core in Verilog

    Language:SystemVerilog7874955267

  • chipsalliance/Cores-VeeR-EH1

    VeeR EH1 core

    Language:SystemVerilog7795797207
  • Leku

    AdevintaSpain/Leku

    :earth_africa: Map location picker component for Android. Based on Google Maps. An alternative to Google Place Picker.

    Language:Kotlin75733152175

  • ultraembedded/cores

    Various HDL (Verilog) IP Cores

    Language:Verilog644475198

  • open-sdr/openwifi-hw

    open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

    Language:Verilog6364059216

  • seldridge/verilog

    Repository for basic (and not so basic) Verilog blocks with high re-use potential

    Language:Verilog519533140

  • fondesa/recycler-view-divider

    A library which configures a divider for a RecyclerView.

    Language:Kotlin50785444

  • ucb-bar/riscv-mini

    Simple RISC-V 3-stage Pipeline in Chisel

    Language:Scala5043928100

  • WangXuan95/FPGA-USB-Device

    An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个FPGA普通IO，而不需要额外的接口芯片。

    Language:Verilog487232181

  • 01walid/awesome-arabic

    A curated list of awesome projects and dev/design resources for supporting Arabic computational needs.

    47638993
  • bootstrap-v4-rtl

    MahdiMajidzadeh/bootstrap-v4-rtl

    RTL edition of bootstrap v4 for rtl languages like Farsi and Arabic

    Language:JavaScript4651748171

  • 4xmen/Web-Package-RTL

    ⚡ Full RTL Package - Bootstrap Responsive Components For Iranian's 🇮🇷

    Language:HTML43371127
  • veryl

    veryl-lang/veryl

    Veryl: A Modern Hardware Description Language

    Language:Rust4131023619

  • erfanmola/DontAskToAsk

    ⭕️ نپرس که بپرسم، فقط بپرس ⭕️

    Language:Vue3734611

  • Nuand/bladeRF-wiphy

    bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem

    Language:VHDL373241349

  • intel/rohd

    The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.

    Language:Dart3551522064

  • pymtl/pymtl3

    Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

    Language:Python354186444
  • tailwindcss-rtl

    20lives/tailwindcss-rtl

    Enabling bidirectional support on tailwindcss framework

    Language:JavaScript34564033

  • duolingo/rtl-viewpager

    ViewPager with RTL support :arrows_counterclockwise:

    Language:Java342312053
  • react-datepicker

    t0gre/react-datepicker

    An easily internationalizable, accessible, mobile-friendly datepicker library for the web, build with styled-components.

    Language:JavaScript32995853