WangXuan95/USTC-RVSoC
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC,包含一个RV32I CPU、一个简单可扩展的总线、一些外设。
SystemVerilogGPL-3.0
Issues
- 0
risc-v支持地址非对齐
#11 opened by SuperR99 - 0
ARTY A7 VGA 的支援
#10 opened by Chiwawachiwawa - 2
请问是普林斯顿架构还是哈佛架构
#8 opened by david4958606 - 4
C语言如何编译成RISC-V机器码并运行?
#7 opened by zchliu - 1
老哥有点秀啊
#2 opened by hyf6661669 - 2
运行USTCRVSoC-tool时发生错误
#6 opened by zchliu - 3
basys3开发板部署
#4 opened by wzc314 - 0
Question for your translater
#5 opened by 0806gcx