risc-v
There are 1698 repositories under risc-v topic.
RT-Thread/rt-thread
RT-Thread is an open source IoT real-time operating system (RTOS).
platformio/platformio-core
Your Gateway to Embedded Software Development Excellence :alien:
tock/tock
A secure embedded operating system for microcontrollers
MichaIng/DietPi
Lightweight justice for your single-board computer!
alibaba/AliOS-Things
面向IoT领域的、高可伸缩的物联网操作系统，可去官网了解更多信息https://www.aliyun.com/product/aliosthings
OpenXiangShan/XiangShan
Open-source high-performance RISC-V processor
chyyuu/os_kernel_lab
OS kernel labs based on Rust/C Lang & RISC-V 64/X86-32
misprit7/computerraria
A fully compliant RISC-V computer made inside the game Terraria
SI-RISCV/e200_opensource
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
mortbopet/Ripes
A graphical processor simulator and assembly editor for the RISC-V ISA
openhwgroup/cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
uxmal/reko
Reko is a binary decompiler.
k2-fsa/sherpa-onnx
Speech-to-text, text-to-speech, and speaker recognition using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, Raspberry Pi, RISC-V, x86_64 servers, websocket server/client, C/C++, Python, Kotlin, C#, Go, NodeJS, Java, Swift, Dart, JavaScript
darklife/darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
larsbrinkhoff/awesome-cpus
All CPU and MCU documentation in one place
risc0/risc0
RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture.
rcore-os/rCore-Tutorial-v3
Let's write an OS which can run on RISC-V in Rust from scratch!
gem5/gem5
The official repository for the gem5 computer-system architecture simulator.
ucb-bar/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
stnolting/neorv32
:desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
renode/renode
Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems
olofk/serv
SERV - The SErial RISC-V CPU
lowRISC/ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
riscv-mcu/e203_hbirdv2
The Ultra-Low Power RISC-V Core
ultraembedded/riscv
RISC-V CPU Core (RV32IM)
TheThirdOne/rars
RARS -- RISC-V Assembler and Runtime Simulator
rcore-os/rCore-Tutorial-Book-v3
A book about how to write OS kernels in Rust easily.
sysprog21/shecc
A self-hosting and educational C optimizing compiler
simdutf/simdutf
Unicode routines (UTF8, UTF16, UTF32) and Base64: billions of characters per second using SSE2, AVX2, NEON, AVX-512, RISC-V Vector Extension. Part of Node.js and Bun.
LekKit/RVVM
The RISC-V Virtual Machine
firesim/firesim
FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
syntacore/scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
riscvarchive/riscv-cores-list
RISC-V Cores, SoC platforms and SoCs
ultraembedded/biriscv
32-bit Superscalar RISC-V CPU
chipsalliance/Cores-VeeR-EH1
VeeR EH1 core
eugene-tarassov/vivado-risc-v
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro