Issues
- 0
__attribute__((__naked__)) usage
#1423 opened by bewimm - 2
image_gen requires bin not elf
#1421 opened by ttsmit - 0
RVFI trace port bus transactions
#1419 opened by michalmonday - 1
[feature request] add Ada support
#1412 opened by ohenley - 3
Recommended approach for DMA peripheral to/from memory?
#1405 opened by kurtjd - 2
- 19
More precise instruction timing documentation
#1297 opened by CharlesAverill - 2
WDT: Seeking clarification on illegal access behavior
#1386 opened by kurtjd - 7
Coremark run in simulation
#1382 opened by mmcheraghi - 3
Vivado BD still shows template neorv32_cfs (XOR/OR demo) instead of my custom neorv32_cfs.vhd — how to correctly bind external CFS for synth and sim?
#1380 opened by albinkoshy1418 - 9
- 2
- 0
[help wanted] add further ISA extensions to TRACER simulation-mode decoding
#1367 opened by stnolting - 5
UART interrupt is not enabled
#1147 opened by stdefeber - 6
AHB-Lite Bus Integration in neorv32_vivado_ip
#1218 opened by Muddassar180009 - 2
More than two cores
#1199 opened by pepijndevos - 10
The uart printf statements block or do not print
#1188 opened by stdefeber - 17
Should AMO be seen as a write or a read operation
#1276 opened by jeras - 2
- 6
Executing hex file in neorv32_tb.vhd
#1351 opened by mmcheraghi - 1
example demo_semihosting fails to link with Zcb extension due to alignment error
#1348 opened by vogma - 3
[User Guide and Datasheet] Version of VHDL is missing
#1343 opened by CyberFox001 - 1
[User Guide] System integration - running TCL script through GUI (Tools -> Run TCL script)
#1340 opened by michalmonday - 3
Burst transfer in cache
#1337 opened by mmcheraghi - 4
Error in item 18 of processor check
#1336 opened by mmcheraghi - 2
- 10
Prioritizing S_RESTART to S_REQUEST in frontend
#1323 opened by mmcheraghi - 10
bootloader fails to build with stack alignment error
#1311 opened by htminuslab - 2
Problem with Cache block size
#1309 opened by 1yacht - 6
FPGA style register file
#1306 opened by mmcheraghi - 14
Boot Modes Not Working with Vivado IP Core, but Works with HDL Implementation
#1203 opened by Muddassar180009 - 3
Consider leveraging VexRISC-V CPU core?
#1242 opened by bitandquit - 17
Instruction fetch from xbus external memory during execution falls into bad 8 bit accesses.
#1269 opened by kurtjensen - 3
[idea] `DMA` bug, `CRC` relevance, `CFS` makeover
#1271 opened by stnolting - 11
A question about RAM base address modification
#1261 opened by mmcheraghi - 7
bootloader jumps to SPI flash loading mode
#1258 opened by mmcheraghi - 2
- 1
[SDI] input not synchronized?
#1223 opened by NikLeberg - 1
PWM prescaler value ignored
#1221 opened by henrikbrixandersen - 3
Makefile error, readlink does not exist in power shell
#1216 opened by ecstrema - 5
Bootloader does not support SPI Flash WP Pin
#1195 opened by jpf91 - 3
JTAG understanding issue
#1198 opened by ecstrema - 6
RISCV_PREFIX must be explicitly set for compilation through stnolting/neorv32/sim container
#1185 opened by Unike267 - 3
Mistake in Bootloader-Makefile USER_FLAGS
#1187 opened by lebruu - 5
[Documentation] SPI register inconsistency
#1164 opened by drgrandios - 1
Boot failure when constructors are used
#1169 opened by bewimm - 1
Internal Bootloader - out of range error
#1170 opened by lebruu - 2
TWD going into idle depends on TX Fifo content
#1157 opened by LukasP46 - 2
demo_clint access faults on the neorv32-setups minimalboot for the radiona ulx3s
#1154 opened by ohenley - 0
interrupt capabilities for the GPIO controller?
#1155 opened by stnolting