Pinned Repositories
fpga-hdl
A set of small Verilog projects, to simulate and implement on FPGA development boards
fri-magisterij
LaTeX templates for theses written at Faculty of Computer and Information Science, University of Ljubljana.
HDLDB
GDB server stub for replaying recorded HDL simulations
preimages-2D
2D cellular automata preimages count&list algorithm
rp32
RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
soc-kit
System on Chip toolkit (Verilog 2001)
sockit_cdc
clock domain crossing FIFO
sockit_owm
SocKit 1-wire (onewire) master
SystemC-UVM
UVM-SystemC Library
TCB
Tightly Coupled Bus, low complexity, high performance system bus.
jeras's Repositories
jeras/rp32
RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
jeras/HDLDB
GDB server stub for replaying recorded HDL simulations
jeras/synthesis-primitives
Observing and optimizing synthesis of common bit manipulation operations for FPGA and ASIC
jeras/TCB
Tightly Coupled Bus, low complexity, high performance system bus.
jeras/vivado_simulator
Evaluation of the Xilinx Vivado simulator
jeras/ADAMS
all digital PLL
jeras/zephyr-qemu-test-app
Zephyr QEMU test app
jeras/cellular-automata-sage-toolkit
Automatically exported from code.google.com/p/cellular-automata-sage-toolkit
jeras/example-systemverilog
jeras/fpga_pio
An attempt to recreate the RP2040 PIO in an FPGA
jeras/HDL-CRC
CRC implementation in HDL languages (VHDL, SystemVerilog)
jeras/jeras.github.io
personal "Rattus Pubis" webpage
jeras/jtag_pulp
jeras/learn-fpga
Learning FPGA, yosys, nextpnr, and RISC-V
jeras/miscelaneous
jeras/Modern-Computer-Architecture-and-Organization-Second-Edition
Modern Computer Architecture and Organization – Second Edition, Published by Packt
jeras/nerv
Naive Educational RISC V processor
jeras/openlane2
The next generation of OpenLane, rewritten from scratch with a modular architecture
jeras/PeakRDL-docgen
Markdown/AsciiDoc documentation generator for the PeakRDL toolchain
jeras/PeakRDL-jinja
Universal code/documentation exporter based on Jinja templates
jeras/PeakRDL-regblock
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
jeras/riscof
jeras/riscv-isa-manual
RISC-V Instruction Set Manual
jeras/SPI-Master---Slave
jeras/sv_fixed_point
SystemVerilog fixed point library
jeras/UHDM-integration-tests
jeras/UHDM-tests
Test for UHDM SystemVerilog plugin for yosys.
jeras/ultrasound_tof
Ultrasonic TOF (Time of Flight) measurement or distance measurement
jeras/UVVM
UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/
jeras/verilator
Verilator open-source SystemVerilog simulator and lint system