Pinned Repositories
fpga-hdl
A set of small Verilog projects, to simulate and implement on FPGA development boards
fri-magisterij
LaTeX templates for theses written at Faculty of Computer and Information Science, University of Ljubljana.
HDLDB
GDB server stub for replaying recorded HDL simulations
preimages-2D
2D cellular automata preimages count&list algorithm
rp32
RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
soc-kit
System on Chip toolkit (Verilog 2001)
sockit_cdc
clock domain crossing FIFO
sockit_owm
SocKit 1-wire (onewire) master
SystemC-UVM
UVM-SystemC Library
TCB
Tightly Coupled Bus, low complexity, high performance system bus.
jeras's Repositories
jeras/soc-kit
System on Chip toolkit (Verilog 2001)
jeras/Terasic_DE1
Demo designs for the Terasic DE1 board
jeras/ecs8
projects related to the ECS8 board
jeras/iverilog
Icarus Verilog