/TCB

Tightly Coupled Bus, low complexity, high performance system bus.

Primary LanguageSystemVerilogApache License 2.0Apache-2.0

WARNING: this project is in an ALPHA stage, not advertized yet. It might already be worth looking at, but the progress status statements are not reliable, and the API-s are not stable yet.

DOC + LIB + VIP + PERI

TCB

This project provides the following parts:

  • Tightly Coupled Bus documentation,
  • reference interconnect library,
  • reference verification library (VIP),
  • reference peripherals.

The purpose of TCB is to fill a niche for a low complexity system bus without unnecessary limitations on throughput.

Implementation status

status description
planed The component should be a part of project, but there is no implementation yet.
VIP (Work In Progress) The implementation is partially done, or it might require

Common shared code

The interface and package are shared across the RTL and verification code for the rest of the code.

module status description
tcb_if done SystemVerilog interface.
tcb_pkg done SystemVerilog package.

VIP (Verification IP)

module status description
tcb_vip_pkg VIP Package containing manager/monitor/subordinate code.
tcb_vip_mem VIP Multi port memory model.
tcb_vip_tb VIP Testbench for core VIP functionality.

Reference implementation library

module status description
tcb_lib_passthrough done Trivial passthrough.
tcb_lib_register planed Register for request/response paths.
tcb_lib_connector planed Interface connector with automatic handling of parameter differences.
tcb_lib_arbiter done Priority arbiter.
tcb_lib_multiplexer done Multiplexer of multiple managers.
tcb_lib_decoder done Address decoder.
tcb_lib_demultiplexer done Demultiplexer of multiple subordinates.
tcb_lib_error done Error response leaf subordinate.

Peripherals

module status description
tcb_gpio WIP GPIO controller.
tcb_uart WIP UART controller.

References

  1. QMEM specification and IP
  2. Open Core Protocol on Wikipedia
  3. CoreConnect from IBM on Wikipedia](https://web.archive.org/web/20090129183058/http://www-01.ibm.com/chips/techlib/techlib.nsf/products/CoreConnect_Bus_Architecture)
  4. Ibex RISC-V core load/store bus interface
  5. NeoRV32 RISC-V core bus interface
  6. AMBA on Wikipedia
  7. AMBA on ARM
  8. Wishbone B4
  9. Pulp Platform Snitch Reqrsp Interface
  10. OpenHW Group OBI (OpenBus Interface)
  11. TileLink 1.8.0, 1.8.1
  12. OpenTitan TileLink IP