systemverilog

There are 995 repositories under systemverilog topic.

  • clash-lang/clash-compiler

    Haskell to VHDL/Verilog/SystemVerilog compiler

    Language:Haskell1.5k54985154
  • verible

    chipsalliance/verible

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    Language:C++1.4k48963215

  • pulp-platform/axi

    AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

    Language:SystemVerilog1.1k39123272

  • hdl-util/hdmi

    Send video/audio over HDMI on an FPGA

    Language:SystemVerilog1.1k4532116

  • splinedrive/kianRiscV

    RISC-V Linux SoC, marchID: 0x2b

    Language:Assembly72828452

  • olofk/edalize

    An abstraction library for interfacing EDA tools

    Language:Python65033166193

  • MikePopoloski/slang

    SystemVerilog compiler and language services

    Language:C++64630696141

  • TerosTechnology/vscode-terosHDL

    VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

    Language:VHDL5802447847

  • WangXuan95/FPGA-FOC

    An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

    Language:Verilog5791414179

  • trivialmips/nontrivial-mips

    NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

    Language:SystemVerilog57727198

  • zachjs/sv2v

    SystemVerilog to Verilog conversion

    Language:Haskell5731627955
  • veryl

    veryl-lang/veryl

    Veryl: A Modern Hardware Description Language

    Language:Rust5501336527

  • dalance/svls

    SystemVerilog language server

    Language:Rust474104431

  • openhwgroup/core-v-verif

    Functional verification project for the CORE-V family of RISC-V cores.

    Language:Assembly46049514228

  • dalance/sv-parser

    SystemVerilog parser library fully compliant with IEEE 1800-2017

    Language:Rust415196555

  • pymtl/pymtl3

    Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

    Language:Python390217148

  • jamieiles/80x86

    80186 compatible SystemVerilog CPU core and FPGA reference design

    Language:C++383261051

  • chipsalliance/Surelog

    SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

    Language:C++3742792068

  • taichi-ishitani/tvip-axi

    AMBA AXI VIP

    Language:SystemVerilog3661639106

  • WangXuan95/USTC-RVSoC

    An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

    Language:SystemVerilog36614875

  • rggen/rggen

    Code generation tool for control and status registers

    Language:Ruby3441415843

  • dalance/svlint

    SystemVerilog linter

    Language:Rust322128633
  • sv-tests

    chipsalliance/sv-tests

    Test suite designed to check compliance with the SystemVerilog standard.

    Language:SystemVerilog3041928075

  • mshr-h/vscode-verilog-hdl-support

    HDL support for VS Code

    Language:TypeScript3021120679

  • Nic30/hdlConvertor

    Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

    Language:C++2852313468

  • tymonx/logic

    CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

    Language:SystemVerilog27332159

  • WangXuan95/FPGA-SDcard-Reader

    An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。

    Language:Verilog2719965

  • WangXuan95/FPGA-ftdi245fifo

    An FPGA-based FT232H/FT600 chip controller for rapid data transmission via USB. 使用FT232H/FT600芯片进行FPGA与电脑之间的高速数据传输。

    Language:Verilog27091485

  • veripool/verilog-mode

    Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.

    Language:SystemVerilog2643057391

  • WangXuan95/FPGA-CAN

    An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。

    Language:Verilog2338469

  • WangXuan95/FPGA-JPEG-LS-encoder

    An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器，可实现高压缩率的无损/近无损图像压缩。

    Language:Verilog2228744

  • pulp-platform/cheshire

    A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

    Language:Verilog206142150

  • chipsalliance/UHDM

    Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

    Language:C++2052011540

  • Nic30/hwt

    VHDL/Verilog/SystemC code generator, simulator API written in python/c++

    Language:Python204184227

  • suoto/hdl_checker

    Repurposing existing HDL tools to help writing better code

    Language:Python195177623

  • Juniper/open-register-design-tool

    Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

    Language:Verilog194448670