chipsalliance/verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
C++NOASSERTION
Issues
- 3
linter cannot find macro defined in a different file
#2173 opened by samimia-swks - 1
All features, can add the option to accept the contents of the file without having to pass in one file at a time.
#2170 opened by 17Reset - 0
- 0
verible.filelist empty file exception
#2178 opened by sconwayaus - 0
VSCode - Generate and maintain verible.filelist
#2177 opened by sconwayaus - 4
Migrate name style rules to regex
#2074 opened by IEncinas10 - 0
automatically comment preprocessor conditionals
#2171 opened by fangism - 2
- 3
VSCode LSP crashes while adding module inputs/outputs
#2146 opened by The-MEO - 0
- 3
- 4
- 0
nix package for mac not available
#2163 opened by thuvasooriya - 0
[unpacked-dimensions-range-ordering] - configuration
#2161 opened by sconwayaus - 0
VSCode can't set binary path in windows
#2154 opened by sconwayaus - 0
- 1
Long `localparam` lines are not formatted
#2156 opened by goekce - 0
Return type using `type(...)` throws syntax error
#2157 opened by goekce - 4
How to use rule for having a begin and end
#2040 opened by muneebullashariff - 0
- 0
verible-verilog-syntax does not support dimensioned parameter in list of parameter assignments
#2152 opened by craigc40 - 1
There is no syntax highlighting in VS Code
#2149 opened by DeflateAwning - 0
Struct signals not checked for `signal-name-style`
#2147 opened by matlupi - 3
How to debug VSCode LS?
#2127 opened by shareefj - 1
Unexpected formatting of interface classes
#2145 opened by sriyerg - 2
[Help or suggestion] How to disable short if-else statements on a single line?
#2053 opened by beyond-fu - 3
- 4
false-positive for CamelCase parameter in a SV module
#2136 opened by jdhaliwa - 0
- 0
- 0
[Feature request] Signal names in the module instantiation (align brackets and add spaces inside)
#2118 opened by alexeykosinov - 0
typedef array of interfaces not supported
#2114 opened by matlupi - 3
uvm-macro-semicolon detects false positives
#2107 opened by matlupi - 0
Property definition with disable iff before event fails
#2108 opened by matlupi - 0
- 0
strict weak ordering problem in autoexpander DependsOn()
#2099 opened by hzeller - 4
Rejected valid signal name
#2076 opened by matlupi - 0
Potential crash when local file is replaced with verilog::VerilogProject::UpdateFileContents()
#2078 opened by hzeller - 4
- 0
How to print original code real line number in ./print_modules.py or ./print_tree.py ?
#2071 opened by shenmufeng - 0
Crash of formatter on a signed wire
#2063 opened by hzeller - 0
[Feature request] Support to add spaces in parentheses/emptyblock/emptyparentheses with formatter
#2054 opened by beyond-fu - 1
How can I parse only verilog and not systemverilog?
#2048 opened by arunpatro - 0
smoke-test-analyzer currently not working.
#2046 opened by hzeller - 0
- 1
Insufficient forbidden-macro documentation
#2041 opened by matlupi - 0
- 1
Weird formatter output when typedef a enum
#2036 opened by ckf104 - 1
nested replication construct rejected syntax
#2037 opened by fangism - 2
Lint configuration rules on nvim
#2035 opened by msebgarcia