Pinned Repositories
dm_control
DeepMind's software stack for physics-based simulation and Reinforcement Learning environments, using MuJoCo.
notcl
Replace Tcl scripting with Python
pydesignflow
Micro-Framework for FPGA / VLSI Design Flow in Python
verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
wavedromScape
wavedrom extension for Inkscape
pancake
:pancakes: Panorama Camera Car Tracking
rsd
RSD: RISC-V Out-of-Order Superscalar Processor
notcl
Replace Tcl scripting with Python
a-kest's Repositories
a-kest/pydesignflow
Micro-Framework for FPGA / VLSI Design Flow in Python
a-kest/dm_control
DeepMind's software stack for physics-based simulation and Reinforcement Learning environments, using MuJoCo.
a-kest/notcl
Replace Tcl scripting with Python
a-kest/verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server