Pinned Repositories
chisel
Chisel: A Modern Hardware Design Language
chisel-template
A template project for beginning new Chisel work
Cores-VeeR-EH1
VeeR EH1 core
f4pga
FOSS Flow For FPGA
firrtl
Flexible Intermediate Representation for RTL
riscv-dv
Random instruction generator for RISC-V processor verification
rocket-chip
Rocket Chip Generator
Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
sv-tests
Test suite designed to check compliance with the SystemVerilog standard.
verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
CHIPS Alliance's Repositories
chipsalliance/chisel
Chisel: A Modern Hardware Design Language
chipsalliance/rocket-chip
Rocket Chip Generator
chipsalliance/verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
chipsalliance/f4pga
FOSS Flow For FPGA
chipsalliance/sv-tests
Test suite designed to check compliance with the SystemVerilog standard.
chipsalliance/Cores-VeeR-EL2
VeeR EL2 Core
chipsalliance/Caliptra
Caliptra IP and firmware for integrated Root of Trust block
chipsalliance/synlig
SystemVerilog synthesis tool
chipsalliance/t1
chipsalliance/caliptra-sw
Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test
chipsalliance/caliptra-rtl
HW Design Collateral for Caliptra RoT IP
chipsalliance/riscv-vector-tests
Unit tests generator for RVV 1.0
chipsalliance/firrtl-spec
The specification for the FIRRTL language
chipsalliance/verilator
Verilator open-source SystemVerilog simulator and lint system
chipsalliance/chisel-nix
Nix template for the chisel-based industrial designing flows.
chipsalliance/verible-linter-action
Automatic SystemVerilog linting in github actions with the help of Verible
chipsalliance/caliptra-dpe
High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs
chipsalliance/chisel-interface
The 'missing header' for Chisel
chipsalliance/homebrew-verible
chipsalliance/adams-bridge
Post-Quantum Cryptography IP Core (Crystals-Dilithium)
chipsalliance/rvdecoderdb
The Scala parser to parse riscv/riscv-opcodes generate
chipsalliance/caliptra-ss
HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
chipsalliance/rocket-pcb
PCB libraries and templates for rocket-chip based FPGA/ASIC designs
chipsalliance/i3c-core
chipsalliance/rocket-uncore
chipsalliance/sv-tests-results
Output of the sv-tests runs.
chipsalliance/chips-alliance-website
chipsalliance/rocket-pcblib
chipsalliance/systolic
A matrix multiplication implementation via systolic array
chipsalliance/synlig-logs