Pinned Repositories
chisel
Chisel: A Modern Hardware Design Language
chisel-template
A template project for beginning new Chisel work
Cores-VeeR-EH1
VeeR EH1 core
f4pga
FOSS Flow For FPGA
firrtl
Flexible Intermediate Representation for RTL
riscv-dv
Random instruction generator for RISC-V processor verification
rocket-chip
Rocket Chip Generator
Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
VeeRwolf
FuseSoC-based SoC for VeeR EH1 and EL2
verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
CHIPS Alliance's Repositories
chipsalliance/chisel
Chisel: A Modern Hardware Design Language
chipsalliance/rocket-chip
Rocket Chip Generator
chipsalliance/verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
chipsalliance/riscv-dv
Random instruction generator for RISC-V processor verification
chipsalliance/firrtl
Flexible Intermediate Representation for RTL
chipsalliance/chisel-template
A template project for beginning new Chisel work
chipsalliance/f4pga
FOSS Flow For FPGA
chipsalliance/VeeRwolf
FuseSoC-based SoC for VeeR EH1 and EL2
chipsalliance/Cores-VeeR-EL2
VeeR EL2 Core
chipsalliance/dromajo
RISC-V RV64GC emulator designed for RTL co-simulation
chipsalliance/UHDM
Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
chipsalliance/Caliptra
Caliptra IP and firmware for integrated Root of Trust block
chipsalliance/t1
chipsalliance/caliptra-rtl
HW Design Collateral for Caliptra RoT IP
chipsalliance/caliptra-sw
Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test
chipsalliance/firrtl-spec
The specification for the FIRRTL language
chipsalliance/verilator
Verilator open-source SystemVerilog simulator and lint system
chipsalliance/diplomacy
chipsalliance/homebrew-verible
chipsalliance/rocket-chip-fpga-shells
Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards
chipsalliance/rocket-chip-inclusive-cache
An RTL generator for a last-level shared inclusive TileLink cache controller
chipsalliance/caliptra-dpe
High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs
chipsalliance/rocket-chip-blocks
RTL blocks compatible with the Rocket Chip Generator
chipsalliance/chisel-interface
The 'missing header' for Chisel
chipsalliance/rocket-pcb
PCB libraries and templates for rocket-chip based FPGA/ASIC designs
chipsalliance/sv-tests-results
Output of the sv-tests runs.
chipsalliance/tac
CHIPS Alliance Technical Advisory Council
chipsalliance/chips-alliance-website
chipsalliance/rocket-pcblib
chipsalliance/verible-actions-common