chipsalliance/firrtl

Issues

• firrtl internal error- caused by java

  #2691 opened 4 months ago by Prasanthyg
  3

• Why this project is deprecated?

  #2671 opened 8 months ago by DavidZyy
  1

• Internal Error when using the loadMemoryFromFileInline

  #2649 opened a year ago by xlgforever
  0

• Firrtl internal exception for adding LoadMemoryFromFile in generators/rocket-chip/src/main/scala/amba/axi4/SRAM.scala

  #2634 opened a year ago by chithize
  0

• Unsupported platform: protoc-3.5.1-osx-aarch_64.exe

  #2539 opened 2 years ago by ilongshan
  4

• Reporting a vulnerability

  #2631 opened a year ago by igibek
  1

• FIRRTL Crash: Internal Error

  #2629 opened a year ago by sehuang
  2

• semantics of multi clock memory

  #2612 opened 2 years ago by wky17
  0

• How to add options while using treadle to make random validif answer?

  #2611 opened 2 years ago by wky17
  2

• How does a memory with multi-writer ports operate when they all write to a same address in the same clk step?

  #2609 opened 2 years ago by wky17
  3

• build.sc: firrtlCrossModule.antlr4Path java.util.NoSuchElementException: empty.head

  #2604 opened 2 years ago by vowstar
  0

• Internal error - Crash

  #2583 opened 2 years ago by sviraaj
  1

• Semantics of DefRegister in FIRRTL

  #2491 opened 2 years ago by Phantom1003
  0

• WDefInstanceConnector support in InstanceKeyGraph

  #2490 opened 2 years ago by Phantom1003
  2

• DeadCodeElimination transform is not working properly.

  #2562 opened 2 years ago by poddar92
  0

• PathNotFoundException in CheckCombLoops transform

  #2547 opened 2 years ago by tymcauley
  0

• syntax error(s) when parsing low Firrtl

  #2537 opened 2 years ago by wky17
  0

• Internal error when loading masked memory from file

  #2492 opened 3 years ago by zyedidia
  1

• Incorrect optimization of a register with a reset

  #2516 opened 2 years ago by youngar
  8

• Annotation deserialization should not rely on "class" coming first

  #2497 opened 3 years ago by fabianschuiki
  2

• simple combination of rem, eq, and mux operators produces "Internal Error! trying to emit unsupported operator: UnknownType"

  #2500 opened 3 years ago by dsw
  1

• `Dedup` causes extra instances to be inlined

  #2498 opened 3 years ago by youngar
  0

• Internal error when running test

  #2484 opened 3 years ago by hutch31
  1

• Why do modulus(%) and compare(===/<=/>=) operators combinations lead to firrtl.FirrtlInternalException?

  #2287 opened 3 years ago by liyewen521
  0

• Failed to emit Verilog when using the modulus operator.

  #2480 opened 3 years ago by gsegura96
  3

• scala.MatchError when using AttributeAnnotation for a module with several instances

  #2479 opened 3 years ago by AlexMontgomerie
  1

• Preset doesn't work with simulation constructs

  #2348 opened 3 years ago by jackkoenig
  0

• Add Compiler Build Information to Output Verilog

  #2461 opened 3 years ago by seldridge
  1

• Missing Constant Folders

  #2432 opened 3 years ago by seldridge
  1

• Truncating the result of signed addition

  #2439 opened 3 years ago by youngar
  3

• (_ BitVec 1) and Bool do not match

  #2436 opened 3 years ago by liuyic00
  2

• Extmodule port name check fails with length-parameterized Vec ports

  #2437 opened 3 years ago by johnsbrew
  2

• RemoveResets Doesn't Look Through Nodes

  #2435 opened 3 years ago by seldridge
  0

• feature request: constant folding for division and remainder

  #2410 opened 3 years ago by ekiwi
  1

• feature request: strength reduction for division or remainder when the denominator is a constant power of two

  #2411 opened 3 years ago by ekiwi
  0

• [RFC] new `cover-values` statement to efficiently count mutually-exclusive events

  #2395 opened 3 years ago by ekiwi
  4

• Optimized Low Firrtl Emitter should not emit `skip` statements

  #2388 opened 3 years ago by ekiwi
  0

• Add option to ignore undeserializable annotations (basically pass them through)

  #2384 opened 3 years ago by jackkoenig
  2

• ReplSeqMem Crashes on Register with Smaller Vec Init Trying to Pad Smaller Type

  #2379 opened 3 years ago by seldridge
  1

• Abstract Reset in Uninstantiated Module Crashes without DCE

  #2373 opened 3 years ago by seldridge
  0

• Verilog Emitter: randomize registers by default

  #2366 opened 3 years ago by ekiwi
  0

• Usage instructions for ReplSeqMemsAnnotation are incorrect

  #2351 opened 3 years ago by mwachs5
  1

• `InlineInstances` invalidates `RemoveWires`

  #2349 opened 3 years ago by ekiwi
  0

• No Deprecation for passes.Legalize https://github.com/chipsalliance/firrtl/pull/2304

  #2345 opened 3 years ago by mwachs5
  0

• Division width in generated verilog

  #2342 opened 3 years ago by davidmetz
  2

• Dead Modules with Abstract Reset Require DCE

  #2337 opened 3 years ago by seldridge
  0

• InlineInstances Incomplete RenameMap for Inlined Modules

  #2327 opened 3 years ago by seldridge
  0

• Not Constant Prop'ing Across Output Ports Used as RHS Values

  #2299 opened 3 years ago by seldridge
  1

• Width of `dshl(a)` inferred less than the width of `a`

  #2296 opened 3 years ago by fabianschuiki
  0

• Multi-dimension IO connection bug

  #2293 opened 3 years ago by sequencer
  2