Pinned Repositories
arbitrary-int
A modern and lightweight implementation of arbitrary integers for Rust
barstools
Useful utilities for BAR projects
chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
chisel
Chisel 3: A Modern Hardware Design Language
circt
Circuit IR Compilers and Tools
constellation
A Chisel RTL generator for network-on-chip interconnects
dotfiles
My collection of configuration files
dsptools
A Library of Chisel3 Tools for Digital Signal Processing
fern
Simple, efficient logging for Rust
riscv-isa-manual
RISC-V Instruction Set Manual
tymcauley's Repositories
tymcauley/arbitrary-int
A modern and lightweight implementation of arbitrary integers for Rust
tymcauley/barstools
Useful utilities for BAR projects
tymcauley/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
tymcauley/chisel
Chisel 3: A Modern Hardware Design Language
tymcauley/circt
Circuit IR Compilers and Tools
tymcauley/constellation
A Chisel RTL generator for network-on-chip interconnects
tymcauley/dotfiles
My collection of configuration files
tymcauley/dsptools
A Library of Chisel3 Tools for Digital Signal Processing
tymcauley/fern
Simple, efficient logging for Rust
tymcauley/firrtl-spec
The specification for the FIRRTL language
tymcauley/llvm-vim-syntax
vim language files for LLVM filetypes
tymcauley/null-ls.nvim
Use Neovim as a language server to inject LSP diagnostics, code actions, and more via Lua.
tymcauley/nvdla-sw
NVDLA SW adjusted for FireSim Linux Simulations
tymcauley/riscv-isa-manual
RISC-V Instruction Set Manual
tymcauley/FFTGenerator
tymcauley/fixedpoint
Chisel Fixed-Point Arithmetic Library
tymcauley/nvdla-workload
Base NVDLA Workload for FireMarshal
tymcauley/nvdla-wrapper
Wraps the NVDLA project for Chipyard integration
tymcauley/nvim-web-devicons
lua `fork` of vim-web-devicons for neovim
tymcauley/prezto
The configuration framework for Zsh
tymcauley/riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
tymcauley/rocket-chip
Rocket Chip Generator
tymcauley/rocket-chip-blocks
RTL blocks compatible with the Rocket Chip Generator
tymcauley/rocket-chip-inclusive-cache
An RTL generator for a last-level shared inclusive TileLink cache controller
tymcauley/rocket-dsp-utils
Tools for integrating DspTools components into a rocket-chip
tymcauley/spike-dasm-rs
Rust implementation of spike's RISC-V disassembler, spike-dasm
tymcauley/testchipip
tymcauley/verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter.
tymcauley/XenOrchestraInstallerUpdater
xen-orchestra automated installer and updater